From 6b909f21af1c012a0de6bc817311c8b93683ee39 Mon Sep 17 00:00:00 2001 From: Kerry Sheh Date: Tue, 7 Feb 2012 20:31:40 +0800 Subject: RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Reviewed-on: http://review.coreboot.org/559 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/northbridge/amd/Kconfig | 1 + src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/cimx/Kconfig | 24 ++ src/northbridge/amd/cimx/Makefile.inc | 20 ++ src/northbridge/amd/cimx/rd890/Kconfig | 33 +++ src/northbridge/amd/cimx/rd890/Makefile.inc | 25 ++ src/northbridge/amd/cimx/rd890/NbPlatform.h | 147 +++++++++++ src/northbridge/amd/cimx/rd890/amd.h | 385 ++++++++++++++++++++++++++++ src/northbridge/amd/cimx/rd890/cbtypes.h | 71 +++++ src/northbridge/amd/cimx/rd890/chip.h | 38 +++ src/northbridge/amd/cimx/rd890/early.c | 113 ++++++++ src/northbridge/amd/cimx/rd890/late.c | 257 +++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 44 ++++ 13 files changed, 1159 insertions(+) create mode 100644 src/northbridge/amd/cimx/Kconfig create mode 100644 src/northbridge/amd/cimx/Makefile.inc create mode 100644 src/northbridge/amd/cimx/rd890/Kconfig create mode 100644 src/northbridge/amd/cimx/rd890/Makefile.inc create mode 100644 src/northbridge/amd/cimx/rd890/NbPlatform.h create mode 100644 src/northbridge/amd/cimx/rd890/amd.h create mode 100644 src/northbridge/amd/cimx/rd890/cbtypes.h create mode 100644 src/northbridge/amd/cimx/rd890/chip.h create mode 100644 src/northbridge/amd/cimx/rd890/early.c create mode 100644 src/northbridge/amd/cimx/rd890/late.c create mode 100644 src/northbridge/amd/cimx/rd890/nb_cimx.h (limited to 'src') diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 4a120ca50b..33e19c2a9f 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig +source src/northbridge/amd/cimx/Kconfig menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index bf96b80c16..c438473b01 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig new file mode 100644 index 0000000000..6751bd4f4f --- /dev/null +++ b/src/northbridge/amd/cimx/Kconfig @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +#Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config AMD_NB_CIMX + bool + default n + +source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc new file mode 100644 index 0000000000..80844c87fe --- /dev/null +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig new file mode 100644 index 0000000000..6731b60fca --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_CIMX_RD890 + bool + default n + select AMD_NB_CIMX + +config REDIRECT_NBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Northbridge CIMX Trace to serial console" + default n + depends on NORTHBRIDGE_AMD_CIMX_RD890 + help + This Option allows you to redirect the AMD Northbridge CIMX + Trace debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc new file mode 100644 index 0000000000..5eaefd128c --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# RD890 Platform Files +romstage-y += early.c + +ramstage-y += late.c + diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h new file mode 100644 index 0000000000..824057ad05 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_PLATFORM_H_ +#define _NB_PLATFORM_H_ + +#define SERIAL_OUT_SUPPORT //enable serial output +#define CIMX_DEBUG + +#ifdef CIMX_DEBUG +#define CIMX_TRACE_SUPPORT +#define CIMX_ASSERT_SUPPORT +#endif + +#ifdef CIMX_TRACE_SUPPORT + #define CIMX_INIT_TRACE(Arguments) + #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable + #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) + #else + #define TRACE_DATA(Ptr, Level) + #define CIMX_TRACE(Argument) + #endif +#else + #define CIMX_TRACE(Argument) + #define CIMX_INIT_TRACE(Arguments) +#endif + +#ifdef CIMX_ASSERT_SUPPORT + #ifdef ASSERT + #undef ASSERT + #define ASSERT CIMX_ASSERT + #endif + #ifdef CIMX_TRACE_SUPPORT + #define CIMX_ASSERT(x) if(!(x)) {\ + LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ + /*__asm {jmp $}; */\ + } + //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + #else + #define CIMX_ASSERT(x) if(!(x)) {\ + /*__asm {jmp $}; */\ + } + #endif +#else + #define CIMX_ASSERT(x) +#endif + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) +#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) + +#ifdef B2_IMAGE +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#else +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#endif + + + +// CIMX configuration parameters +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 +#else +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#endif + + + +#define CIMX_S3_SAVE 1 +#include "cbtypes.h" +#include + +#include "amd.h" //cimx typedef +#include +#include "amdAcpiLib.h" +#include "amdAcpiMadt.h" +#include "amdAcpiIvrs.h" +#include "amdSbLib.h" +#include "nbPcie.h" + +//must put before the nbType.h +#include "platform_cfg.h" /*platform dependented configuration */ +#include "nbType.h" + +#include "nbLib.h" +#include "nbDef.h" +#include "nbInit.h" +#include "nbHtInit.h" +#include "nbIommu.h" +#include "nbEventLog.h" +#include "nbRegisters.h" +#include "nbPcieAspm.h" +#include "nbPcieLinkWidth.h" +#include "nbPcieHotplug.h" +#include "nbPciePortRemap.h" +#include "nbPcieWorkarounds.h" +#include "nbPcieCplBuffers.h" +#include "nbPciePllControl.h" +#include "nbMiscInit.h" +#include "nbIoApic.h" +#include "nbPcieSb.h" +#include "nbRecovery.h" +#include "nbMaskedMemoryInit.h" + + +#define FIX_PTR_ADDR(x, y) x + +#define TRACE_ALWAYS 0xffffffff + +#define AmdNbDispatcher NULL + +#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_NBPOR_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_MISC 0xFFFFFFFF + +#endif + diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h new file mode 100644 index 0000000000..d99f90f575 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +#include "cbtypes.h" + + +#define VOLATILE volatile +#define CALLCONV +#define ROMDATA +#define CIMXAPI EFIAPI + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + + +// AGESA Structures +/// The standard header AMD NB UEFI drivers +typedef struct _AMD_CONFIG_PARAMS { + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; /// + +/* +typedef int64_t __int64; +typedef void VOID; +typedef uint32_t UINTN;// +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; +*/ +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN;// +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; + +#define TRUE 1 +#define FALSE 0 +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +//porting.h +#ifndef CONST +#define CONST const +#endif +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h new file mode 100644 index 0000000000..c2f985bacc --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_RD890_CHIP_H_ +#define _CIMX_RD890_CHIP_H_ + +extern struct chip_operations northbridge_amd_cimx_rd890_ops; + +/** + * RD890 specific device configuration + */ +struct northbridge_amd_cimx_rd890_config +{ + u8 gpp1_configuration; + u8 gpp2_configuration; + u8 gpp3a_configuration; + u16 port_enable; +}; + +#endif /* _CIMX_RD890_CHIP_H_ */ + diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c new file mode 100644 index 0000000000..8008223669 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "nb_cimx.h" + + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void) +{ + u32 nb_dev; + u32 mask; + u32 val; + AMD_NB_CONFIG_BLOCK cfg_block; + AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; + AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); + + nb_cfg->ConfigPtr = &cfg_ptr; + nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + val = (1 << 2) | (1 << 3); /*GPP1*/ + val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ + val |= (1 << 18) | (1 << 19); /*GPP2*/ + val |= (1 << 20); /*GPP3b*/ + mask = ~val; + LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, + AccessS3SaveWidth32, + mask, + val, + nb_cfg); +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdPowerOnResetInit entry point. + */ +void nb_Poweron_Init(void) +{ + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + AGESA_STATUS status; + + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); + CIMX_INIT_TRACE(); + CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); + } + + status = AmdPowerOnResetInit(&gConfig); + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); +} + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdHtInit entry point. + */ +void nb_Ht_Init(void) +{ + AGESA_STATUS status; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + u32 i; + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + //Initialize HT structure + LibSystemApiCall(AmdHtInitializer, &gConfig); + for (i = 0; i < MAX_NB_COUNT; i ++) { + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); + } + } + + status = LibSystemApiCall(AmdHtInit, &gConfig); + printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); +} + +void nb_S3_Init(void) +{ + //TODO +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c new file mode 100644 index 0000000000..208e5f1d77 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -0,0 +1,257 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "NbPlatform.h" +#include "nb_cimx.h" +#include "rd890_cfg.h" + + +/** + * Global RD890 CIMX Configuration structure + */ +static NB_CONFIG nb_cfg[MAX_NB_COUNT]; +static HT_CONFIG ht_cfg[MAX_NB_COUNT]; +static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; +static AMD_NB_CONFIG_BLOCK gConfig; + + +/** + * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ +void nb_Pcie_Early_Init(void) +{ + LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); +} + +void nb_Pcie_Late_Init(void) +{ + LibSystemApiCall(AmdPcieLateInit, &gConfig); +} + +void nb_Early_Post_Init(void) +{ + LibSystemApiCall(AmdEarlyPostInit, &gConfig); +} + +void nb_Mid_Post_Init(void) +{ + LibSystemApiCall(AmdMidPostInit, &gConfig); +} + +void nb_Late_Post_Init(void) +{ + LibSystemApiCall(AmdLatePostInit, &gConfig); +} + +static void rd890_enable(device_t dev) +{ + u32 address = 0; + u32 mask; + u32 val; + u32 devfn; + u32 port; + AMD_NB_CONFIG *NbConfigPtr = NULL; + + u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ + address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + NbConfigPtr = &(gConfig.Northbridges[nb_index]); + + devfn = dev->path.pci.devfn; + port = devfn >> 3; + printk(BIOS_INFO, "rd890_enable "); + printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", + 0, (devfn >> 3), (devfn & 0x07), dev->enabled); + if (port != 0) { + if (dev->enabled) { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; + } else { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + } + } + + switch (port) { + case 0x0: /* Root Complex, and ClkConfig */ + + if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ + break; + } + + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + /* NOTE: not use LibNbCallBack */ + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + break; + + case 0x2: /* Gpp1 Port0 */ + case 0x3: /* Gpp1 Port1 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x4: /* Gpp3a Port0 */ + case 0x5: /* Gpp3a Port1 */ + case 0x6: /* Gpp3a Port2 */ + case 0x7: /* Gpp3a Port3 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x8: /* SB ALink */ + mask = ~(1 << 6); + val = (dev->enabled ? 1 : 0) << 6; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x9: /* Gpp3a Port4 */ + case 0xa: /* Gpp3a Port5 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xb: /* Gpp2 Port0 */ + case 0xc: /* Gpp2 Port1 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xd: /* Gpp3b */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + + /* Init NB at Early Post */ + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init();// + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); + break; + + default: + printk(BIOS_INFO, "Buggy Device Tree\n"); + break; + } +} + +struct chip_operations northbridge_amd_cimx_rd890_ops = { + CHIP_NAME("ATI rd890") + .enable_dev = rd890_enable, +}; + + +static void ioapic_init(struct device *dev) +{ + u32 ioapic_base; + + pci_write_config32(dev, 0xF8, 0x1); + ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + setup_ioapic(ioapic_base, 1); +} + +static void rd890_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void rd890_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = rd890_read_resource, + .set_resources = rd890_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; + +static const struct pci_driver ht_driver_rd890tv __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +}; + +static const struct pci_driver ht_driver_rd890 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890_HT, +}; + +static const struct pci_driver ht_driver_990fx __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_990FX_HT, +}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h new file mode 100644 index 0000000000..a6f77db1a8 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_CIMX_H_ +#define _NB_CIMX_H_ + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void); + +/** + * Northbridge CIMX entries point + */ +void nb_Poweron_Init(void); +void nb_Ht_Init(void); +void nb_S3_Init(void); +void nb_Early_Post_Init(void); +void nb_Mid_Post_Init(void); +void nb_Late_Post_Init(void); +void nb_Pcie_Early_Init(void); +void nb_Pcie_Late_Init(void); + +#endif//_RD890_EARLY_H_ + -- cgit v1.2.3