From 6b7b016b6006feb22b48a44b25fd71f1f39ad9cb Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 01:45:50 +0100 Subject: mb/sapphire/pureplatinumh61: Don't write BUC and beyond The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/sapphire/pureplatinumh61/early_init.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src') diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index be665617a4..9a1b6856ff 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -26,11 +26,6 @@ void mainboard_pch_lpc_setup(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } -void mainboard_late_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 }, -- cgit v1.2.3