From 6b6c94bacc13a374abc8069aec7da074121015b9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 25 Nov 2017 00:45:23 +0100 Subject: intel/gma: fix RPNFREQ_VAL bitmask gma.c of Nehalem was copied from Sandy/Ivy Bridge, so fix it there too. Tested on lenovo/x230. Since both the bit that was masked wrongly and the one that wasn't masked, but sould have been, are 0, the behaviour on lenovo/x230 doesn't change. Change-Id: I5f51c4929df83f948fcb7dc06e07ac3cc4ccf4f2 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/22596 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/nehalem/gma.c | 5 +++-- src/northbridge/intel/sandybridge/gma.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 0c681ccc83..4dcbfb30ee 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -488,10 +488,11 @@ static void gma_pm_init_pre_vbios(struct device *dev) } /* 12: Normal Frequency Request */ - /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ + /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ + /* only the lower 7 bits are used and shifted left by 25 */ reg32 = MCHBAR32(0x5998); reg32 >>= 16; - reg32 &= 0xef; + reg32 &= 0x7f; reg32 <<= 25; gtt_write(0xa008, reg32); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 61b9008467..74aabf9e66 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -498,10 +498,11 @@ static void gma_pm_init_pre_vbios(struct device *dev) } /* 12: Normal Frequency Request */ - /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ + /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ + /* only the lower 7 bits are used and shifted left by 25 */ reg32 = MCHBAR32(0x5998); reg32 >>= 16; - reg32 &= 0xef; + reg32 &= 0x7f; reg32 <<= 25; gtt_write(0xa008, reg32); -- cgit v1.2.3