From 6b45ee44a9bbccb4dc42ea454aa20ef7d02a9fd1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 12 May 2017 11:43:57 +0530 Subject: soc/intel/skylake: Add option to enable/disable EIST Set MSR 0x1A0 bit[16] based on EIST config option. Default Hardware Managed P-state (HWP) also known as Intel Speed Shift is enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/19676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/skylake/acpi.c | 7 ++++--- src/soc/intel/skylake/chip.h | 6 ++++++ src/soc/intel/skylake/chip_fsp20.c | 3 +++ src/soc/intel/skylake/cpu.c | 7 ++++++- 4 files changed, 19 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index e8d0c1683a..64438bdd80 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -523,9 +523,10 @@ void generate_cpu_entries(device_t device) generate_c_state_entries(is_s0ix_enable, max_c_state); - /* Generate P-state tables */ - generate_p_state_entries(core_id, - cores_per_package); + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, + cores_per_package); acpigen_pop_len(); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b474ca22a1..43c921e8e6 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -459,6 +459,12 @@ struct soc_intel_skylake_config { /* Enable SGX feature */ u8 sgx_enable; + + /* Enable/Disable EIST + * 1b - Enabled + * 0b - Disabled + */ + u8 eist_enable; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2d9b864629..8a7cb210e0 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -261,6 +261,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable PMC XRAM read */ tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; + /* Enable/Disable EIST */ + tconfig->Eist = config->eist_enable; + soc_irq_settings(params); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index c472617b0f..057241327b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -245,12 +245,17 @@ static void configure_isst(void) static void configure_misc(void) { + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + if (conf->eist_enable) + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + else + msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ -- cgit v1.2.3