From 6ab7e5e0906b02b29e9634343f3e9ca722a1088e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 31 May 2017 18:21:59 +0200 Subject: nb/intel/sandybridge/raminit: Advertise correct frequency As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the reference clock can be 100Mhz. Decode the register and use the reference clock to calculate the selected DDR frequency. Tested on Lenovo T430. Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/19995 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 4b92d18cf0..b50555646d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -123,14 +123,17 @@ static void fill_smbios17(ramctr_timing *ctrl) static void report_memory_config(void) { u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; - int i; + int i, refclk; addr_decoder_common = MCHBAR32(0x5000); addr_decode_ch[0] = MCHBAR32(0x5004); addr_decode_ch[1] = MCHBAR32(0x5008); + refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; + + printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); -- cgit v1.2.3