From 6aaa4f9198666b28f6081458f4d5184167305f99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 4 Jul 2023 09:22:39 +0300 Subject: emulation/qemu-q35: Enable ECAM earlier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align implementation with real hardwares, such that ECAM (PCI configuration via MMIO) is available for use when console is initialised. Change-Id: I288991f31d3f1678132aa4315168c09eabbbe98d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/76206 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) Reviewed-by: Nicholas Chin Reviewed-by: Felix Held --- src/mainboard/emulation/qemu-q35/bootblock.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index bacdae8685..d40ff0f98d 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -7,7 +7,7 @@ #include "q35.h" -static void bootblock_northbridge_init(void) +void bootblock_soc_early_init(void) { /* * The "io" variant of the config access is explicitly used to @@ -24,9 +24,6 @@ static void bootblock_northbridge_init(void) const uint32_t pciexbar = make_pciexbar(); pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, 0); pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, pciexbar); - - if (CONFIG(BOOTBLOCK_CONSOLE)) - mainboard_machine_check(); } static void bootblock_southbridge_init(void) @@ -40,6 +37,8 @@ static void bootblock_southbridge_init(void) void bootblock_soc_init(void) { - bootblock_northbridge_init(); + if (CONFIG(BOOTBLOCK_CONSOLE)) + mainboard_machine_check(); + bootblock_southbridge_init(); } -- cgit v1.2.3