From 6a6550be4f80296210893c05d83b0545e8567c2d Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Mon, 24 Apr 2023 17:37:13 -0700 Subject: soc/intel/alderlake: Disable SaGV reordering Disable re-ordering SaGv point on warm reset so that most performant SaGv point is picked after memory training and boot time is reduced. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721 Reviewed-by: Eric Lai Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/chipset.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index e41cd842c8..5d717b8e54 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -93,6 +93,9 @@ chip soc/intel/alderlake # Reduce the size of BasicMemoryTests to speed up the boot time. register "lower_basic_mem_test_size" = "true" + # Disable SaGV reordering operation to start with SaGV point 4 and reduce boot time. + register "disable_sagv_reorder" = "true" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. -- cgit v1.2.3