From 68fb5437f9680428cbb7cf39c4a73911671a6359 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 24 Nov 2022 08:38:19 +0100 Subject: mb/siemens/mc_ehl2: Disable L1 prefetcher As for mainboard mc_ehl1, a hard real-time dependency is also required for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: I07b27dd672533e693a6c2987d16f54333850760e Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index e1c297274c..74d0f26e42 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -135,6 +135,9 @@ chip soc/intel/elkhartlake .vcc_low_high_us = 50, }" + # Disable L1 prefetcher for real-time demands + register "L1_prefetcher_disable" = "true" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- cgit v1.2.3