From 68cf57cf33141edcc8b4b1250b099884e0553457 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 17:12:32 +0100 Subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense. Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Furquan Shaikh --- src/mainboard/51nb/x210/devicetree.cb | 1 - src/mainboard/google/eve/devicetree.cb | 1 - src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/glados/devicetree.cb | 1 - src/mainboard/google/poppy/variants/atlas/devicetree.cb | 1 - src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nami/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 1 - src/mainboard/google/poppy/variants/rammus/devicetree.cb | 1 - src/mainboard/google/poppy/variants/soraka/devicetree.cb | 1 - src/mainboard/libretrend/lt1000/devicetree.cb | 1 - src/mainboard/protectli/vault_kbl/devicetree.cb | 1 - src/mainboard/purism/librem_skl/devicetree.cb | 1 - src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 1 - src/soc/intel/skylake/chip.h | 3 --- src/soc/intel/skylake/romstage/romstage.c | 2 +- 17 files changed, 1 insertion(+), 19 deletions(-) (limited to 'src') diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 0e408f808e..43f272e5a8 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "1" register "SataMode" = "0" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index f8a92d88de..0e76de140f 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -35,7 +35,6 @@ chip soc/intel/skylake register "gen3_dec" = "0x00fc0901" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 430334af5f..8c31f9ac70 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -64,7 +64,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4f8beefd65..127334e1ba 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4fd71d5cf6..a14e927b0f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 93836421f0..4bfac6d78b 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 65ecc8f3f1..25d720e584 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ec55645a84..9563298518 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 6b58e0b048..899990de0b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 841823116c..ff117c8aa2 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8e5caf3fb2..6a37b8a4bc 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f6e73c6bd6..9fedde5db8 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d8e68a2373..abbfda4223 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "tcc_offset" = "5" # TCC of 95C # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 6d98772af7..c59df40518 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 8f3e0d6bc3..44b352359d 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,7 +23,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4d92410b65..f4744c9631 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -90,9 +90,6 @@ struct soc_intel_skylake_config { /* Whether to ignore VT-d support of the SKU */ int ignore_vtd; - /* Probeless Trace function */ - u8 ProbelessTrace; - /* * System Agent dynamic frequency configuration * When enabled memory will be trained at two different frequencies. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 79fb46425d..c826187c4b 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -216,7 +216,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->Rmt; -- cgit v1.2.3