From 66faf0c286e30e22eb4eb120b95f34e2723ebd32 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 13 May 2018 13:32:56 +0200 Subject: sb/intel/i82801dx: Get rid of device_t MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use of device_t has been abandoned in ramstage. Change-Id: I36f064b67f14556e38b41b7f64c3e27d8d935367 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26255 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/i82801dx/i82801dx.c | 4 ++-- src/southbridge/intel/i82801dx/i82801dx.h | 2 +- src/southbridge/intel/i82801dx/lpc.c | 10 +++++----- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index a4eb0481c5..cc70fdd9e8 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -20,7 +20,7 @@ #include #include "i82801dx.h" -void i82801dx_enable(device_t dev) +void i82801dx_enable(struct device *dev) { unsigned int index = 0; uint8_t bHasDisableBit = 0; @@ -28,7 +28,7 @@ void i82801dx_enable(device_t dev) // all 82801dbm devices are in bus 0 unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc - device_t lpc_dev = dev_find_slot(0, devfn); // 0 + struct device *lpc_dev = dev_find_slot(0, devfn); // 0 if (!lpc_dev) return; diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 14ca28f9aa..8c7da55ff1 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -32,7 +32,7 @@ #if !defined(__ASSEMBLER__) #if !defined(__SIMPLE_DEVICE__) #include "chip.h" -extern void i82801dx_enable(device_t dev); +extern void i82801dx_enable(struct device *dev); #else void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 0f0bbcfeac..925251da2a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -81,7 +81,7 @@ static void i82801dx_enable_serial_irqs(struct device *dev) (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); } -static void i82801dx_pirq_init(device_t dev) +static void i82801dx_pirq_init(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -96,7 +96,7 @@ static void i82801dx_pirq_init(device_t dev) pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); } -static void i82801dx_power_options(device_t dev) +static void i82801dx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -175,7 +175,7 @@ static void i82801dx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void gpio_init(device_t dev) +static void gpio_init(struct device *dev) { /* This should be done in romstage.c already */ pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); @@ -217,7 +217,7 @@ static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801dx_lpc_decode_en(device_t dev) +static void i82801dx_lpc_decode_en(struct device *dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -301,7 +301,7 @@ static void lpc_init(struct device *dev) enable_hpet(dev); } -static void i82801dx_lpc_read_resources(device_t dev) +static void i82801dx_lpc_read_resources(struct device *dev) { struct resource *res; -- cgit v1.2.3