From 65bb5434f6eb9e1f0f72a52958193b38057cfad7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 3 Jul 2018 14:59:50 +0200 Subject: src: Get rid of non-local header treated as local Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27331 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/amd/car/post_cache_as_ram.c | 2 +- src/cpu/amd/family_10h-family_15h/model_10xxx_init.c | 2 +- src/cpu/intel/haswell/romstage.c | 10 +++++----- src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl | 2 +- src/mainboard/asus/kcma-d8/dsdt.asl | 8 ++++---- src/mainboard/asus/kfsn4-dre/dsdt.asl | 4 ++-- src/mainboard/asus/kgpe-d16/dsdt.asl | 8 ++++---- src/mainboard/asus/p2b-ls/dsdt.asl | 6 +++--- src/mainboard/asus/p2b/dsdt.asl | 6 +++--- src/southbridge/intel/fsp_rangeley/romstage.c | 2 +- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- 11 files changed, 26 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index a96811365a..75a0aba1e7 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -31,7 +31,7 @@ #include "cpu/amd/car/disable_cache_as_ram.c" // For set_sysinfo_in_ram() -#include "northbridge/amd/amdfam10/raminit.h" +#include #if CONFIG_RAMTOP <= 0x100000 #error "You need to set CONFIG_RAMTOP greater than 1M" diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 58364d4cac..50406744bb 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -24,7 +24,7 @@ #include #include #include -#include "northbridge/amd/amdfam10/amdfam10.h" +#include #include #include #include diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index b30d4af8b0..c74bfd6ff0 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -37,12 +37,12 @@ #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include #endif -#include "haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/me.h" +#include +#include +#include +#include #include +#include "haswell.h" static inline void reset_system(void) { diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl index 54ead92d47..f8709a4323 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl @@ -230,5 +230,5 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMDF10", "AMDACPI ", 100925440) Z00A, 8 } - #include "northbridge/amd/amdfam10/amdfam10_util.asl" + #include } diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index 5754d7c2bc..b6dd211afa 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -39,8 +39,8 @@ DefinitionBlock ( 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" - #include "southbridge/amd/sr5650/acpi/sr5650.asl" + #include + #include /* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -427,7 +427,7 @@ DefinitionBlock ( { Name (_ADR, 0x00110000) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/sata.asl" + #include } /* 0:12.0 SP5100 USB 0 */ @@ -477,7 +477,7 @@ DefinitionBlock ( { Name (_ADR, 0x00140001) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/ide.asl" + #include } /* 0:14.3 SP5100 LPC */ diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl index 575715cf66..f3d59ce470 100644 --- a/src/mainboard/asus/kfsn4-dre/dsdt.asl +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -39,7 +39,7 @@ DefinitionBlock ( 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" + #include /* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -404,7 +404,7 @@ DefinitionBlock ( Return (Local3) } -#include "southbridge/nvidia/ck804/acpi/ck804.asl" +#include /* PCI Routing Table Access */ Method (_PRT, 0, NotSerialized) { diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index ab6547ceb5..7b78b5de2e 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -39,8 +39,8 @@ DefinitionBlock ( 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" - #include "southbridge/amd/sr5650/acpi/sr5650.asl" + #include + #include /* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -427,7 +427,7 @@ DefinitionBlock ( { Name (_ADR, 0x00110000) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/sata.asl" + #include } /* 0:12.0 SP5100 USB 0 */ @@ -477,7 +477,7 @@ DefinitionBlock ( { Name (_ADR, 0x00140001) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/ide.asl" + #include } /* 0:14.3 SP5100 LPC */ diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 304a0f4e7d..73d9508ccc 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -116,7 +116,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Return (0x0B) } } - #include "southbridge/intel/i82371eb/acpi/intx.asl" + #include PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) @@ -174,7 +174,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, }) - #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" + #include /* Begin southbridge block */ Device (PX40) @@ -230,7 +230,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Return (BUF1) } } - #include "southbridge/intel/i82371eb/acpi/i82371eb.asl" + #include } Device (PX43) { diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 8ddbf28418..93f6afe83f 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -112,7 +112,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Return (0x0B) } } - #include "southbridge/intel/i82371eb/acpi/intx.asl" + #include PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) @@ -160,7 +160,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, }) - #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" + #include /* Begin southbridge block */ Device (PX40) @@ -216,7 +216,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Return (BUF1) } } - #include "southbridge/intel/i82371eb/acpi/i82371eb.asl" + #include } Device (PX43) { diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 74df69112c..2f598d88d5 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -27,7 +27,7 @@ #include #include #include -#include "northbridge/intel/fsp_rangeley/northbridge.h" +#include #include "southbridge/intel/fsp_rangeley/soc.h" #include "southbridge/intel/fsp_rangeley/gpio.h" #include "southbridge/intel/fsp_rangeley/romstage.h" diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index cb4bc7efb6..4c45613487 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -27,7 +27,7 @@ #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #else -#include "southbridge/intel/common/gpio.h" +#include #endif const struct rcba_config_instruction pch_early_config[] = { -- cgit v1.2.3