From 650a56f7bbf4127e5cf420f979d31d7e0ecc808e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 2 Jan 2020 00:16:03 +0100 Subject: mb/hp/folio_9470m: Transform into variant Tested with BUILD_TIMELESS=1, binary does not change. Change-Id: I65696c5739469b33253c22c1d5a65cc31ef3a421 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38095 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/hp/folio_9470m/Kconfig | 46 ---- src/mainboard/hp/folio_9470m/Kconfig.name | 2 - src/mainboard/hp/folio_9470m/Makefile.inc | 21 -- src/mainboard/hp/folio_9470m/acpi/ec.asl | 16 -- src/mainboard/hp/folio_9470m/acpi/platform.asl | 27 --- src/mainboard/hp/folio_9470m/acpi/superio.asl | 1 - src/mainboard/hp/folio_9470m/acpi_tables.c | 27 --- src/mainboard/hp/folio_9470m/board_info.txt | 7 - src/mainboard/hp/folio_9470m/cmos.default | 6 - src/mainboard/hp/folio_9470m/cmos.layout | 116 ---------- src/mainboard/hp/folio_9470m/data.vbt | Bin 4280 -> 0 bytes src/mainboard/hp/folio_9470m/devicetree.cb | 107 --------- src/mainboard/hp/folio_9470m/dsdt.asl | 44 ---- src/mainboard/hp/folio_9470m/early_init.c | 55 ----- src/mainboard/hp/folio_9470m/gma-mainboard.ads | 33 --- src/mainboard/hp/folio_9470m/gpio.c | 240 --------------------- src/mainboard/hp/folio_9470m/hda_verb.c | 47 ---- src/mainboard/hp/folio_9470m/mainboard.c | 28 --- src/mainboard/hp/snb_ivb_laptops/Kconfig | 3 + src/mainboard/hp/snb_ivb_laptops/Kconfig.name | 13 ++ .../variants/folio_9470m/board_info.txt | 7 + .../snb_ivb_laptops/variants/folio_9470m/data.vbt | Bin 0 -> 4280 bytes .../variants/folio_9470m/devicetree.cb | 107 +++++++++ .../variants/folio_9470m/early_init.c | 55 +++++ .../variants/folio_9470m/gma-mainboard.ads | 33 +++ .../hp/snb_ivb_laptops/variants/folio_9470m/gpio.c | 240 +++++++++++++++++++++ .../variants/folio_9470m/hda_verb.c | 47 ++++ 27 files changed, 505 insertions(+), 823 deletions(-) delete mode 100644 src/mainboard/hp/folio_9470m/Kconfig delete mode 100644 src/mainboard/hp/folio_9470m/Kconfig.name delete mode 100644 src/mainboard/hp/folio_9470m/Makefile.inc delete mode 100644 src/mainboard/hp/folio_9470m/acpi/ec.asl delete mode 100644 src/mainboard/hp/folio_9470m/acpi/platform.asl delete mode 100644 src/mainboard/hp/folio_9470m/acpi/superio.asl delete mode 100644 src/mainboard/hp/folio_9470m/acpi_tables.c delete mode 100644 src/mainboard/hp/folio_9470m/board_info.txt delete mode 100644 src/mainboard/hp/folio_9470m/cmos.default delete mode 100644 src/mainboard/hp/folio_9470m/cmos.layout delete mode 100644 src/mainboard/hp/folio_9470m/data.vbt delete mode 100644 src/mainboard/hp/folio_9470m/devicetree.cb delete mode 100644 src/mainboard/hp/folio_9470m/dsdt.asl delete mode 100644 src/mainboard/hp/folio_9470m/early_init.c delete mode 100644 src/mainboard/hp/folio_9470m/gma-mainboard.ads delete mode 100644 src/mainboard/hp/folio_9470m/gpio.c delete mode 100644 src/mainboard/hp/folio_9470m/hda_verb.c delete mode 100644 src/mainboard/hp/folio_9470m/mainboard.c create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/board_info.txt create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/data.vbt create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/devicetree.cb create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c (limited to 'src') diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig deleted file mode 100644 index b40ca2554f..0000000000 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -if BOARD_HP_FOLIO_9470M - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select EC_HP_KBC1126 - select GFX_GMA_INTERNAL_IS_LVDS - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT - select HAVE_OPTION_TABLE - select INTEL_GMA_HAVE_VBT - select INTEL_INT15 - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_USES_IFD_GBE_REGION - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_C216 - select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT - -config MAINBOARD_DIR - string - default "hp/folio_9470m" - -config MAINBOARD_PART_NUMBER - string - default "EliteBook Folio 9470m" - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config VGA_BIOS_ID - string - default "8086,0166" - -config MAX_CPUS - int - default 8 - -config USBDEBUG_HCD_INDEX - int - default 0 -endif diff --git a/src/mainboard/hp/folio_9470m/Kconfig.name b/src/mainboard/hp/folio_9470m/Kconfig.name deleted file mode 100644 index 92dd985a4e..0000000000 --- a/src/mainboard/hp/folio_9470m/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_HP_FOLIO_9470M - bool "EliteBook Folio 9470m" diff --git a/src/mainboard/hp/folio_9470m/Makefile.inc b/src/mainboard/hp/folio_9470m/Makefile.inc deleted file mode 100644 index 1d258758be..0000000000 --- a/src/mainboard/hp/folio_9470m/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/hp/folio_9470m/acpi/ec.asl b/src/mainboard/hp/folio_9470m/acpi/ec.asl deleted file mode 100644 index ac65fb399f..0000000000 --- a/src/mainboard/hp/folio_9470m/acpi/ec.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Iru Cai - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include diff --git a/src/mainboard/hp/folio_9470m/acpi/platform.asl b/src/mainboard/hp/folio_9470m/acpi/platform.asl deleted file mode 100644 index fe0f936a61..0000000000 --- a/src/mainboard/hp/folio_9470m/acpi/platform.asl +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_WAK,1) -{ - \_SB.PCI0.LPCB.EC0.ACPI = 1 - \_SB.PCI0.LPCB.EC0.SLPT = 0 - - Return(Package(){0,0}) -} - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC0.SLPT = Arg0 -} diff --git a/src/mainboard/hp/folio_9470m/acpi/superio.asl b/src/mainboard/hp/folio_9470m/acpi/superio.asl deleted file mode 100644 index f2b35ba9c1..0000000000 --- a/src/mainboard/hp/folio_9470m/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/src/mainboard/hp/folio_9470m/acpi_tables.c b/src/mainboard/hp/folio_9470m/acpi_tables.c deleted file mode 100644 index 114f6e1228..0000000000 --- a/src/mainboard/hp/folio_9470m/acpi_tables.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - // the lid is open by default. - gnvs->lids = 1; - - gnvs->tcrt = 100; - gnvs->tpsv = 90; -} diff --git a/src/mainboard/hp/folio_9470m/board_info.txt b/src/mainboard/hp/folio_9470m/board_info.txt deleted file mode 100644 index 77ffa22d05..0000000000 --- a/src/mainboard/hp/folio_9470m/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: laptop -Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9470m-ultrabook/5271146/product-info -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Release year: 2013 diff --git a/src/mainboard/hp/folio_9470m/cmos.default b/src/mainboard/hp/folio_9470m/cmos.default deleted file mode 100644 index 455dc1cda9..0000000000 --- a/src/mainboard/hp/folio_9470m/cmos.default +++ /dev/null @@ -1,6 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -gfx_uma_size=32M diff --git a/src/mainboard/hp/folio_9470m/cmos.layout b/src/mainboard/hp/folio_9470m/cmos.layout deleted file mode 100644 index f1526f34c9..0000000000 --- a/src/mainboard/hp/folio_9470m/cmos.layout +++ /dev/null @@ -1,116 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -421 1 e 9 sata_mode - -# coreboot config options: cpu -#424 8 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 5 r 0 unused - -440 8 h 0 volume - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M - -# ----------------------------------------------------------------- -checksums - -checksum 392 447 984 diff --git a/src/mainboard/hp/folio_9470m/data.vbt b/src/mainboard/hp/folio_9470m/data.vbt deleted file mode 100644 index d28896e8c2..0000000000 Binary files a/src/mainboard/hp/folio_9470m/data.vbt and /dev/null differ diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb deleted file mode 100644 index e04ab67a5c..0000000000 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ /dev/null @@ -1,107 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2018 Bill Xie -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.link_frequency_270_mhz" = "1" - register "gfx.ndid" = "3" - register "gfx.use_spread_spectrum_clock" = "1" - register "gpu_cpu_backlight" = "0x00000d9c" - register "gpu_dp_b_hotplug" = "4" - register "gpu_dp_c_hotplug" = "4" - register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" - register "gpu_panel_power_backlight_off_delay" = "2000" - register "gpu_panel_power_backlight_on_delay" = "2000" - register "gpu_panel_power_cycle_delay" = "5" - register "gpu_panel_power_down_delay" = "230" - register "gpu_panel_power_up_delay" = "300" - register "gpu_pch_backlight" = "0x0d9c0d9c" - device cpu_cluster 0x0 on - chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0x0 on end - device lapic 0xacac off end - end - end - device domain 0x0 on - subsystemid 0x103c 0x18df inherit - - device pci 00.0 on end # Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" - register "docking_supported" = "0" - # mailbox at 0x200/0x201 and PM1 at 0x220 - register "gen1_dec" = "0x007c0201" - register "gen2_dec" = "0x000c0101" - register "gen3_dec" = "0x00fcfe01" - register "gen4_dec" = "0x000402e9" - register "gpi6_routing" = "2" - register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" - register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x3" - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" - - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 SDHCI - device pci 1c.3 on end # PCIe Port #4 WLAN - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge - chip ec/hp/kbc1126 - register "ec_data_port" = "0x62" - register "ec_cmd_port" = "0x66" - register "ec_ctrl_reg" = "0x81" - register "ec_fan_ctrl_value" = "0x44" - device pnp ff.1 off end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/hp/folio_9470m/dsdt.asl b/src/mainboard/hp/folio_9470m/dsdt.asl deleted file mode 100644 index 81f45c155e..0000000000 --- a/src/mainboard/hp/folio_9470m/dsdt.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20141018 // OEM revision -) -{ - #include "acpi/platform.asl" - #include - #include - /* global NVS and variables. */ - #include - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - #include - #include - } - } -} diff --git a/src/mainboard/hp/folio_9470m/early_init.c b/src/mainboard/hp/folio_9470m/early_init.c deleted file mode 100644 index ba507cc249..0000000000 --- a/src/mainboard/hp/folio_9470m/early_init.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* SSP1: dock */ - { 1, 1, 0 }, /* SSP2: left, EHCI Debug */ - { 1, 1, 1 }, /* SSP3: right back side */ - { 1, 1, 1 }, /* SSP4: right front side */ - { 1, 0, 2 }, /* B0P5 */ - { 1, 0, 2 }, /* B0P6: wlan USB */ - { 0, 0, 3 }, /* B0P7 */ - { 1, 1, 3 }, /* B0P8: smart card reader */ - { 1, 1, 4 }, /* B1P1: fingerprint reader */ - { 0, 0, 4 }, /* B1P2: (EHCI Debug, not connected) */ - { 1, 1, 5 }, /* B1P3: Camera */ - { 0, 0, 5 }, /* B1P4 */ - { 1, 1, 6 }, /* B1P5: wwan USB */ - { 0, 0, 6 }, /* B1P6 */ -}; - -void bootblock_mainboard_early_init(void) -{ - kbc1126_enter_conf(); - kbc1126_mailbox_init(); - kbc1126_kbc_init(); - kbc1126_ec_init(); - kbc1126_pm1_init(); - kbc1126_exit_conf(); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/folio_9470m/gma-mainboard.ads b/src/mainboard/hp/folio_9470m/gma-mainboard.ads deleted file mode 100644 index e45320f36e..0000000000 --- a/src/mainboard/hp/folio_9470m/gma-mainboard.ads +++ /dev/null @@ -1,33 +0,0 @@ --- --- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP1, - DP2, - DP3, - HDMI1, - HDMI2, - HDMI3, - Analog, - Internal); - -end GMA.Mainboard; diff --git a/src/mainboard/hp/folio_9470m/gpio.c b/src/mainboard/hp/folio_9470m/gpio.c deleted file mode 100644 index 292180c4d1..0000000000 --- a/src/mainboard/hp/folio_9470m/gpio.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio2 = GPIO_MODE_GPIO, - .gpio3 = GPIO_MODE_GPIO, - .gpio4 = GPIO_MODE_GPIO, - .gpio5 = GPIO_MODE_NATIVE, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_GPIO, - .gpio10 = GPIO_MODE_GPIO, - .gpio11 = GPIO_MODE_GPIO, - .gpio12 = GPIO_MODE_NATIVE, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_GPIO, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_GPIO, - .gpio17 = GPIO_MODE_GPIO, - .gpio18 = GPIO_MODE_GPIO, - .gpio19 = GPIO_MODE_GPIO, - .gpio20 = GPIO_MODE_GPIO, - .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, - .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, - .gpio30 = GPIO_MODE_NATIVE, - .gpio31 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_OUTPUT, - .gpio3 = GPIO_DIR_OUTPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio29 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_reset = { - .gpio24 = GPIO_RESET_RSMRST, - .gpio30 = GPIO_RESET_RSMRST, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio4 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio7 = GPIO_INVERT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, - .gpio33 = GPIO_MODE_GPIO, - .gpio34 = GPIO_MODE_GPIO, - .gpio35 = GPIO_MODE_GPIO, - .gpio36 = GPIO_MODE_GPIO, - .gpio37 = GPIO_MODE_GPIO, - .gpio38 = GPIO_MODE_GPIO, - .gpio39 = GPIO_MODE_GPIO, - .gpio40 = GPIO_MODE_GPIO, - .gpio41 = GPIO_MODE_GPIO, - .gpio42 = GPIO_MODE_GPIO, - .gpio43 = GPIO_MODE_GPIO, - .gpio44 = GPIO_MODE_GPIO, - .gpio45 = GPIO_MODE_NATIVE, - .gpio46 = GPIO_MODE_GPIO, - .gpio47 = GPIO_MODE_GPIO, - .gpio48 = GPIO_MODE_GPIO, - .gpio49 = GPIO_MODE_GPIO, - .gpio50 = GPIO_MODE_GPIO, - .gpio51 = GPIO_MODE_GPIO, - .gpio52 = GPIO_MODE_GPIO, - .gpio53 = GPIO_MODE_GPIO, - .gpio54 = GPIO_MODE_GPIO, - .gpio55 = GPIO_MODE_GPIO, - .gpio56 = GPIO_MODE_GPIO, - .gpio57 = GPIO_MODE_GPIO, - .gpio58 = GPIO_MODE_NATIVE, - .gpio59 = GPIO_MODE_GPIO, - .gpio60 = GPIO_MODE_GPIO, - .gpio61 = GPIO_MODE_GPIO, - .gpio62 = GPIO_MODE_NATIVE, - .gpio63 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_INPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio47 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_INPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_INPUT, - .gpio56 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_OUTPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio33 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_reset = { -}; - -static const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, - .gpio65 = GPIO_MODE_GPIO, - .gpio66 = GPIO_MODE_GPIO, - .gpio67 = GPIO_MODE_GPIO, - .gpio68 = GPIO_MODE_GPIO, - .gpio69 = GPIO_MODE_GPIO, - .gpio70 = GPIO_MODE_GPIO, - .gpio71 = GPIO_MODE_GPIO, - .gpio72 = GPIO_MODE_GPIO, - .gpio73 = GPIO_MODE_NATIVE, - .gpio74 = GPIO_MODE_NATIVE, - .gpio75 = GPIO_MODE_NATIVE, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_OUTPUT, - .gpio71 = GPIO_DIR_OUTPUT, - .gpio72 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, - .gpio72 = GPIO_LEVEL_LOW, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_reset = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - .reset = &pch_gpio_set1_reset, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - .reset = &pch_gpio_set3_reset, - }, -}; diff --git a/src/mainboard/hp/folio_9470m/hda_verb.c b/src/mainboard/hp/folio_9470m/hda_verb.c deleted file mode 100644 index 03caeb271e..0000000000 --- a/src/mainboard/hp/folio_9470m/hda_verb.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -const u32 cim_verb_data[] = { - 0x111d76e0, /* Codec Vendor / Device ID: IDT */ - 0x103c18df, /* Subsystem ID */ - 11, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x103c18df), - AZALIA_PIN_CFG(0, 0x0a, 0x21011030), - AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), - AZALIA_PIN_CFG(0, 0x0c, 0x03a11020), - AZALIA_PIN_CFG(0, 0x0d, 0x90170110), - AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), - AZALIA_PIN_CFG(0, 0x0f, 0x2181102e), - AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), - AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), - AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), - AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), - - 0x80862806, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(3, 0x80860101), - AZALIA_PIN_CFG(3, 0x05, 0x18560010), - AZALIA_PIN_CFG(3, 0x06, 0x58560020), - AZALIA_PIN_CFG(3, 0x07, 0x18560030), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/folio_9470m/mainboard.c b/src/mainboard/hp/folio_9470m/mainboard.c deleted file mode 100644 index 058701e33a..0000000000 --- a/src/mainboard/hp/folio_9470m/mainboard.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Bill Xie - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index 62489cb851..c6b218f839 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -38,6 +38,7 @@ config VARIANT_DIR default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P default "8770w" if BOARD_HP_8770W + default "folio_9470m" if BOARD_HP_FOLIO_9470M config MAINBOARD_PART_NUMBER string @@ -46,6 +47,7 @@ config MAINBOARD_PART_NUMBER default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P default "EliteBook 8770w" if BOARD_HP_8770W + default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M config DEVICETREE string @@ -72,5 +74,6 @@ config USBDEBUG_HCD_INDEX default 1 if BOARD_HP_8460P default 2 if BOARD_HP_8470P default 2 if BOARD_HP_8770W + default 0 if BOARD_HP_FOLIO_9470M endif diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index 2eedbf10dd..4ae7b9b83d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -69,3 +69,16 @@ config BOARD_HP_8770W select MAINBOARD_USES_IFD_GBE_REGION select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_LPC47N217 + +config BOARD_HP_FOLIO_9470M + bool "EliteBook Folio 9470m" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_16384 + select GFX_GMA_INTERNAL_IS_LVDS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/board_info.txt new file mode 100644 index 0000000000..77ffa22d05 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9470m-ultrabook/5271146/product-info +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2013 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/data.vbt b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/data.vbt new file mode 100644 index 0000000000..d28896e8c2 Binary files /dev/null and b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/data.vbt differ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/devicetree.cb new file mode 100644 index 0000000000..e04ab67a5c --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/devicetree.cb @@ -0,0 +1,107 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Bill Xie +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000d9c" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x0d9c0d9c" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x103c 0x18df inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + # mailbox at 0x200/0x201 and PM1 at 0x220 + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 SDHCI + device pci 1c.3 on end # PCIe Port #4 WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x44" + device pnp ff.1 off end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c new file mode 100644 index 0000000000..ba507cc249 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/early_init.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* SSP1: dock */ + { 1, 1, 0 }, /* SSP2: left, EHCI Debug */ + { 1, 1, 1 }, /* SSP3: right back side */ + { 1, 1, 1 }, /* SSP4: right front side */ + { 1, 0, 2 }, /* B0P5 */ + { 1, 0, 2 }, /* B0P6: wlan USB */ + { 0, 0, 3 }, /* B0P7 */ + { 1, 1, 3 }, /* B0P8: smart card reader */ + { 1, 1, 4 }, /* B1P1: fingerprint reader */ + { 0, 0, 4 }, /* B1P2: (EHCI Debug, not connected) */ + { 1, 1, 5 }, /* B1P3: Camera */ + { 0, 0, 5 }, /* B1P4 */ + { 1, 1, 6 }, /* B1P5: wwan USB */ + { 0, 0, 6 }, /* B1P6 */ +}; + +void bootblock_mainboard_early_init(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads new file mode 100644 index 0000000000..e45320f36e --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gma-mainboard.ads @@ -0,0 +1,33 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c new file mode 100644 index 0000000000..292180c4d1 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/gpio.c @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c new file mode 100644 index 0000000000..03caeb271e --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/hda_verb.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x111d76e0, /* Codec Vendor / Device ID: IDT */ + 0x103c18df, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c18df), + AZALIA_PIN_CFG(0, 0x0a, 0x21011030), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x2181102e), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; -- cgit v1.2.3