From 640a41f3ee938b794b140218921e0fd63b1d9235 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 16 Nov 2024 09:54:14 +0530 Subject: soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique This commit adds an assertion to ensure that the values of pmc_/gpe0_dw0, pmc_/gpe0_dw1, and pmc_/gpe0_dw2 in the soc_intel__config structure are unique. This check helps to catch potential configuration errors early on, preventing unexpected behavior during system initialization. TEST=Built and booted normally. No assertion failure observed. Able to catch the hidden issue due to overlapping Tier 1 GPE configuration. [DEBUG] CPU: Intel(R) Core(TM) 3 N355 [DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001a [DEBUG] CPU: AES supported, TXT supported, VT supported ... ... [DEBUG] MCH: device id 4617 (rev 00) is Alderlake-N [DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU [DEBUG] IGD: device id 46d3 (rev 00) is Twinlake GT1 [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/pmutil.c', line 163 Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/85161 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- src/soc/intel/alderlake/pmutil.c | 11 +++++++++++ src/soc/intel/apollolake/pmutil.c | 11 +++++++++++ src/soc/intel/cannonlake/pmutil.c | 11 +++++++++++ src/soc/intel/elkhartlake/pmutil.c | 11 +++++++++++ src/soc/intel/jasperlake/pmutil.c | 11 +++++++++++ src/soc/intel/meteorlake/pmutil.c | 11 +++++++++++ src/soc/intel/pantherlake/pmutil.c | 12 ++++++++++++ src/soc/intel/skylake/pmutil.c | 11 +++++++++++ src/soc/intel/tigerlake/pmutil.c | 11 +++++++++++ 9 files changed, 100 insertions(+) (limited to 'src') diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 050fd5bf88..60d6e10984 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -154,12 +154,23 @@ uint32_t *soc_pmc_etr_addr(void) return (uint32_t *)(soc_read_pmc_base() + ETR); } +static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config) +{ + bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_alderlake_config *config; config = config_of_soc(); + pmc_gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->pmc_gpe0_dw0; *dw1 = config->pmc_gpe0_dw1; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 8d9af926d6..5366ca8baf 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -138,12 +138,23 @@ void soc_clear_pm_registers(uintptr_t pmc_bar) write32p(pmc_bar + GEN_PMCON1, gen_pmcon1 & ~RPS); } +static void gpe0_different_values(const struct soc_intel_apollolake_config *config) +{ + bool result = (config->gpe0_dw1 != config->gpe0_dw2) && + (config->gpe0_dw1 != config->gpe0_dw3) && + (config->gpe0_dw2 != config->gpe0_dw3); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_apollolake_config *config; config = config_of_soc(); + gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->gpe0_dw1; *dw1 = config->gpe0_dw2; diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index ed0aecec2c..63eed164c4 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -148,11 +148,22 @@ uint32_t *soc_pmc_etr_addr(void) return (uint32_t *)(soc_read_pmc_base() + ETR); } +static void gpe0_different_values(const struct soc_intel_cannonlake_config *config) +{ + bool result = (config->gpe0_dw0 != config->gpe0_dw1) && + (config->gpe0_dw0 != config->gpe0_dw2) && + (config->gpe0_dw1 != config->gpe0_dw2); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; config = config_of_soc(); + gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->gpe0_dw0; *dw1 = config->gpe0_dw1; diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 2618798f38..a862bdd6e2 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -147,12 +147,23 @@ uint32_t *soc_pmc_etr_addr(void) return (uint32_t *)(soc_read_pmc_base() + ETR); } +static void pmc_gpe0_different_values(const struct soc_intel_elkhartlake_config *config) +{ + bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_elkhartlake_config *config; config = config_of_soc(); + pmc_gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->pmc_gpe0_dw0; *dw1 = config->pmc_gpe0_dw1; diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index f94232a98a..569eac7ea8 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -147,12 +147,23 @@ uint32_t *soc_pmc_etr_addr(void) return (uint32_t *)(soc_read_pmc_base() + ETR); } +static void pmc_gpe0_different_values(const struct soc_intel_jasperlake_config *config) +{ + bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_jasperlake_config *config; config = config_of_soc(); + pmc_gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->pmc_gpe0_dw0; *dw1 = config->pmc_gpe0_dw1; diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 8e91b2778a..154c3bef97 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -150,12 +150,23 @@ uint32_t *soc_pmc_etr_addr(void) return (uint32_t *)(soc_read_pmc_base() + ETR); } +static void pmc_gpe0_different_values(const struct soc_intel_meteorlake_config *config) +{ + bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_meteorlake_config *config; config = config_of_soc(); + pmc_gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->pmc_gpe0_dw0; *dw1 = config->pmc_gpe0_dw1; diff --git a/src/soc/intel/pantherlake/pmutil.c b/src/soc/intel/pantherlake/pmutil.c index 888bb562f8..306d834c5d 100644 --- a/src/soc/intel/pantherlake/pmutil.c +++ b/src/soc/intel/pantherlake/pmutil.c @@ -145,6 +145,15 @@ uint32_t *soc_pmc_etr_addr(void) return (uint32_t *)(soc_read_pmc_base() + ETR); } +static void pmc_gpe0_different_values(const struct soc_intel_pantherlake_config *config) +{ + bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_pantherlake_config *config; @@ -154,6 +163,9 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) printk(BIOS_ERR, "Configuration could not be retrieved.\n"); return; } + + pmc_gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->pmc_gpe0_dw0; *dw1 = config->pmc_gpe0_dw1; diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 5e7d5438d9..ed1ab8be6b 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -154,12 +154,23 @@ uint32_t *soc_pmc_etr_addr(void) return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); } +static void gpe0_different_values(const struct soc_intel_skylake_config *config) +{ + bool result = (config->gpe0_dw0 != config->gpe0_dw1) && + (config->gpe0_dw0 != config->gpe0_dw2) && + (config->gpe0_dw1 != config->gpe0_dw2); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_skylake_config *config; config = config_of_soc(); + gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->gpe0_dw0; *dw1 = config->gpe0_dw1; diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index cd22942bd7..7903264b88 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -153,12 +153,23 @@ uint32_t *soc_pmc_etr_addr(void) return (uint32_t *)(soc_read_pmc_base() + ETR); } +static void pmc_gpe0_different_values(const struct soc_intel_tigerlake_config *config) +{ + bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && + (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); + + assert(result); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_tigerlake_config *config; config = config_of_soc(); + pmc_gpe0_different_values(config); + /* Assign to out variable */ *dw0 = config->pmc_gpe0_dw0; *dw1 = config->pmc_gpe0_dw1; -- cgit v1.2.3