From 64011880240cea5a3f8b1177853c7992a2d99ea8 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 15 Jul 2016 13:31:09 -0700 Subject: soc/intel/common: Add reset_prepare() for common reset Some Intel SoC may need preparation before reset can be properly handled. Add callback that chip/soc code can implement. BUG=chrome-os-partner:55055 Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/15720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/include/reset.h | 3 ++- src/soc/intel/common/reset.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/include/reset.h b/src/include/reset.h index 95ba608254..67f58db81f 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -10,5 +10,6 @@ void soft_reset(void); void cpu_reset(void); /* Some Intel SoCs use a special reset that is specific to SoC */ void global_reset(void); - +/* Some Intel SoCs may need to prepare/wait before reset */ +void reset_prepare(void); #endif diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 79547c6edb..08f36b6560 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -25,8 +25,17 @@ #define RST_CPU (1 << 2) #define SYS_RST (1 << 1) +#ifdef __ROMCC__ +#define WEAK +#else +#define WEAK __attribute__((weak)) +#endif + +void WEAK reset_prepare(void) { /* do nothing */ } + void hard_reset(void) { + reset_prepare(); /* S0->S5->S0 trip. */ outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); while (1) @@ -35,6 +44,7 @@ void hard_reset(void) void soft_reset(void) { + reset_prepare(); /* PMC_PLTRST# asserted. */ outb(RST_CPU | SYS_RST, RST_CNT); while (1) @@ -43,6 +53,7 @@ void soft_reset(void) void cpu_reset(void) { + reset_prepare(); /* Sends INIT# to CPU */ outb(RST_CPU, RST_CNT); while (1) -- cgit v1.2.3