From 621a8d69d9c7d5eb86e409e7cdee665eaf845040 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 28 Mar 2022 17:24:52 +0200 Subject: mb/amd/chausie/devicetree: update PCI root ports Only enable the PCIe root ports that have corresponding DXIO descriptors and also update the comments to have them match the actual hardware configuration. Signed-off-by: Felix Held Change-Id: I378c620abb6e52de680669b6edd228874153e399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162 Reviewed-by: Raul Rangel Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) --- src/mainboard/amd/chausie/devicetree.cb | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 7f37be2128..85e9c08f7e 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -28,12 +28,9 @@ chip soc/amd/sabrina device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # NVMe - device ref gpp_bridge_1 on end - device ref gpp_bridge_2 on end # WWAN - device ref gpp_bridge_3 on end # LAN - device ref gpp_bridge_4 on end # WLAN - device ref gpp_bridge_5 on end + device ref gpp_bridge_0 on end # GBE + device ref gpp_bridge_1 on end # WIFI + device ref gpp_bridge_2 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) -- cgit v1.2.3