From 61f44127f0c06688343fdfa3f518a58b4efe170c Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 25 Jun 2021 11:24:38 -0600 Subject: soc/amd/cezanne: Start loading APOB asynchronously This enables COOP_MULTITASKING (i.e., multiple stacks single CPU). This will allow the APOB to start loading while FSP-S executes. BUG=b:179699789 TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms to a few uS. Starting APOB preload APOB thread running spi_dma_readat_dma: start: dest: 0xcb7aa640, offset: 0x0, size: 65536 took 0 us to acquire mutex start_spi_dma_transaction: dest: 0xcb7aa640, offset: 0x0, remaining: 65536 spi_dma_readat_dma: end: dest: 0xcb7aa640, offset: 0x0, size: 65536, remaining: 0 waiting for thread took 0 us APOB valid copy is already in flash Signed-off-by: Raul E Rangel Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea Reviewed-on: https://review.coreboot.org/c/coreboot/+/56234 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Kconfig | 2 ++ src/soc/amd/cezanne/fsp_s_params.c | 11 ++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 71cca6a11b..5da70f4e0b 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -18,6 +18,7 @@ config SOC_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE + select COOP_MULTITASKING select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -69,6 +70,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI select SSE2 + select TIMER_QUEUE select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index ae51f9254a..96dc61bf80 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include +#include static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { @@ -13,4 +14,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSP_S_CONFIG *scfg = &supd->FspsConfig; fsp_assign_vbios_upds(scfg); + + /* + * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB + * before FSP-S was loaded, we would introduce contention onto the SPI bus and + * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs + * no SPI operations, we can read the APOB while FSP-S executes. + */ + start_apob_cache_read(); } -- cgit v1.2.3