From 60f0f1b18f87332a569ced6c8744a1572517ba39 Mon Sep 17 00:00:00 2001 From: Joseph Smith Date: Fri, 29 May 2009 13:45:22 +0000 Subject: enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge. Signed-off-by: Joseph Smith Acked-by: Ronald G. Minnich Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/asus/mew-am/Config.lb | 5 +++-- src/mainboard/asus/mew-vm/Config.lb | 3 +++ src/mainboard/msi/ms6178/Config.lb | 3 +++ src/mainboard/nec/powermate2000/Config.lb | 3 +++ src/mainboard/rca/rm4100/Config.lb | 3 +++ src/mainboard/thomson/ip1000/Config.lb | 3 +++ src/southbridge/intel/i82801xx/chip.h | 2 ++ src/southbridge/intel/i82801xx/i82801xx_ide.c | 19 +++++++++++++------ 8 files changed, 33 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb index 8756d296b8..e4de52b970 100644 --- a/src/mainboard/asus/mew-am/Config.lb +++ b/src/mainboard/asus/mew-am/Config.lb @@ -82,6 +82,9 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end # Chipset Graphics Controller (CGC) chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O @@ -126,8 +129,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 1f.3 on end # SMbus device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) device pci 1f.6 off end # AC'97 modem (N/A) - #register "ide0_enable" = "1" - #register "ide1_enable" = "1" end end end diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb index a4a061bbe1..cada58f7ae 100644 --- a/src/mainboard/asus/mew-vm/Config.lb +++ b/src/mainboard/asus/mew-vm/Config.lb @@ -103,6 +103,9 @@ chip northbridge/intel/i82810 #end end chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on # PCI Bridge #chip drivers/pci/onboard # device pci 1.0 on end diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb index bfaf8f6f43..773d813922 100644 --- a/src/mainboard/msi/ms6178/Config.lb +++ b/src/mainboard/msi/ms6178/Config.lb @@ -82,6 +82,9 @@ chip northbridge/intel/i82810 # Northbridge # end end chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge chip superio/winbond/w83627hf # Super I/O diff --git a/src/mainboard/nec/powermate2000/Config.lb b/src/mainboard/nec/powermate2000/Config.lb index facf500b26..1388ea41d6 100644 --- a/src/mainboard/nec/powermate2000/Config.lb +++ b/src/mainboard/nec/powermate2000/Config.lb @@ -82,6 +82,9 @@ chip northbridge/intel/i82810 # Northbridge # end end chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) diff --git a/src/mainboard/rca/rm4100/Config.lb b/src/mainboard/rca/rm4100/Config.lb index e11b4d19dc..458d44d23c 100644 --- a/src/mainboard/rca/rm4100/Config.lb +++ b/src/mainboard/rca/rm4100/Config.lb @@ -89,6 +89,9 @@ chip northbridge/intel/i82830 # Northbridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1d.0 on end # USB UHCI Controller #1 device pci 1d.1 on end # USB UHCI Controller #2 device pci 1d.2 on end # USB UHCI Controller #3 diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb index f26ae532d2..5cb29aa7db 100644 --- a/src/mainboard/thomson/ip1000/Config.lb +++ b/src/mainboard/thomson/ip1000/Config.lb @@ -89,6 +89,9 @@ chip northbridge/intel/i82830 # Northbridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1d.0 on end # USB UHCI Controller #1 device pci 1d.1 on end # USB UHCI Controller #2 device pci 1d.2 on end # USB UHCI Controller #3 diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801xx/chip.h index d86c07e8e0..d159aa2be0 100644 --- a/src/southbridge/intel/i82801xx/chip.h +++ b/src/southbridge/intel/i82801xx/chip.h @@ -43,6 +43,8 @@ struct southbridge_intel_i82801xx_config { uint8_t pirqf_routing; uint8_t pirqg_routing; uint8_t pirqh_routing; + uint8_t ide0_enable; + uint8_t ide1_enable; }; extern struct chip_operations southbridge_intel_i82801xx_ops; diff --git a/src/southbridge/intel/i82801xx/i82801xx_ide.c b/src/southbridge/intel/i82801xx/i82801xx_ide.c index f9ba3903e3..4173cc6a75 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_ide.c +++ b/src/southbridge/intel/i82801xx/i82801xx_ide.c @@ -27,29 +27,36 @@ #include #include "i82801xx.h" +typedef struct southbridge_intel_i82801xx_config config_t; + static void ide_init(struct device *dev) { + /* Get the chip configuration */ + config_t *config = dev->chip_info; + /* TODO: Needs to be tested for compatibility with ICH5(R). */ /* Enable IDE devices so the Linux IDE driver will work. */ uint16_t ideTimingConfig; - int enable_primary = 1; - int enable_secondary = 1; ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (enable_primary) { + if (!config || config->ide0_enable) { /* Enable primary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE0 "); + printk_debug("IDE0: Primary IDE interface is enabled\n"); + } else { + printk_info("IDE0: Primary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (enable_secondary) { + if (!config || config->ide1_enable) { /* Enable secondary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE1 "); + printk_debug("IDE1: Secondary IDE interface is enabled\n"); + } else { + printk_info("IDE1: Secondary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); } -- cgit v1.2.3