From 60c619f6a3c0fbe2f53095a029cd07a11f5cf5e1 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 16 Jul 2020 16:35:27 -0600 Subject: soc/intel/jasperlake: Move tco_configure to bootblock Similar to CB:43313 (SHA bb50c672278), it seems possible for the same problem to come up on jasperlake. Again, it should be harmless to configure the TCO device earlier in the boot flow. Signed-off-by: Tim Wawrzynczak Change-Id: If95e46124660b4ed457434f727c9f9f7b02b0327 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43539 Reviewed-by: Aaron Durbin Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/bootblock/bootblock.c | 4 ++++ src/soc/intel/jasperlake/romstage/pch.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index 54ad85a82e..e7d97c50bf 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -25,4 +26,7 @@ void bootblock_soc_init(void) { report_platform_info(); pch_init(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); } diff --git a/src/soc/intel/jasperlake/romstage/pch.c b/src/soc/intel/jasperlake/romstage/pch.c index e800ce50bd..9fd8a1e43e 100644 --- a/src/soc/intel/jasperlake/romstage/pch.c +++ b/src/soc/intel/jasperlake/romstage/pch.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include void pch_init(void) { - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); } -- cgit v1.2.3