From 5fe9aa6ba9c5cc0ceb18f40509d7961d4b4a600e Mon Sep 17 00:00:00 2001 From: Igor Bagnucki Date: Mon, 14 Dec 2020 14:52:50 +0100 Subject: soc/ibm/power9/*: add file structure for SOC Boot device is stubbed to be able to build boards without errors. Change-Id: Ie74b1e34f9aebe151d0fdb0e95c003510fd864c3 Signed-off-by: Igor Bagnucki Signed-off-by: Krystian Hebel Signed-off-by: Sergii Dmytruk Reviewed-on: https://review.coreboot.org/c/coreboot/+/67062 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/ibm/power9/Kconfig | 14 ++++++++++++++ src/soc/ibm/power9/Makefile.mk | 17 +++++++++++++++++ src/soc/ibm/power9/bootblock.c | 7 +++++++ src/soc/ibm/power9/cbmem.c | 15 +++++++++++++++ src/soc/ibm/power9/chip.c | 16 ++++++++++++++++ src/soc/ibm/power9/rom_media.c | 8 ++++++++ src/soc/ibm/power9/romstage.c | 12 ++++++++++++ src/soc/ibm/power9/timer.c | 8 ++++++++ 8 files changed, 97 insertions(+) create mode 100644 src/soc/ibm/power9/Kconfig create mode 100644 src/soc/ibm/power9/Makefile.mk create mode 100644 src/soc/ibm/power9/bootblock.c create mode 100644 src/soc/ibm/power9/cbmem.c create mode 100644 src/soc/ibm/power9/chip.c create mode 100644 src/soc/ibm/power9/rom_media.c create mode 100644 src/soc/ibm/power9/romstage.c create mode 100644 src/soc/ibm/power9/timer.c (limited to 'src') diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig new file mode 100644 index 0000000000..9f3323b63b --- /dev/null +++ b/src/soc/ibm/power9/Kconfig @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_IBM_POWER9 + bool + select ARCH_BOOTBLOCK_PPC64 + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 + help + This SoC is the minimal template working on POWER9 Talos II platform. + +if SOC_IBM_POWER9 + # nothing here yet +endif diff --git a/src/soc/ibm/power9/Makefile.mk b/src/soc/ibm/power9/Makefile.mk new file mode 100644 index 0000000000..84a40f9a34 --- /dev/null +++ b/src/soc/ibm/power9/Makefile.mk @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_IBM_POWER9),y) + +bootblock-y += bootblock.c +bootblock-y += rom_media.c + +romstage-y += cbmem.c +romstage-y += rom_media.c +romstage-y += romstage.c + +ramstage-y += cbmem.c +ramstage-y += chip.c +ramstage-y += rom_media.c +ramstage-y += timer.c + +endif diff --git a/src/soc/ibm/power9/bootblock.c b/src/soc/ibm/power9/bootblock.c new file mode 100644 index 0000000000..86217285b9 --- /dev/null +++ b/src/soc/ibm/power9/bootblock.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void bootblock_soc_early_init(void) +{ +} diff --git a/src/soc/ibm/power9/cbmem.c b/src/soc/ibm/power9/cbmem.c new file mode 100644 index 0000000000..9543c45848 --- /dev/null +++ b/src/soc/ibm/power9/cbmem.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +uintptr_t cbmem_top_chipset(void) +{ + /* + * Smallest reported to be working (but not officially supported) DIMM is + * 4GB. This means that we always have at least as much available. Last + * 256MB are reserved for hostboot/coreboot (OCC and HOMER images). + * + * TODO: implement this properly after RAM is detected. + */ + return 4ull * GiB - 256 * MiB; +} diff --git a/src/soc/ibm/power9/chip.c b/src/soc/ibm/power9/chip.c new file mode 100644 index 0000000000..f93c21600a --- /dev/null +++ b/src/soc/ibm/power9/chip.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static void enable_soc_dev(struct device *dev) +{ + ram_range(dev, 0, 0, cbmem_top_chipset()); + /* This is for OCC and HOMER images */ + reserved_ram_range(dev, 1, cbmem_top_chipset(), 256 * MiB); +} + +struct chip_operations soc_ibm_power9_ops = { + .name = "POWER9", + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/ibm/power9/rom_media.c b/src/soc/ibm/power9/rom_media.c new file mode 100644 index 0000000000..c07af1bbf0 --- /dev/null +++ b/src/soc/ibm/power9/rom_media.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const struct region_device *boot_device_ro(void) +{ + return NULL; +} diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c new file mode 100644 index 0000000000..4a3ed8304c --- /dev/null +++ b/src/soc/ibm/power9/romstage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void main(void) +{ + console_init(); + cbmem_initialize_empty(); + run_ramstage(); +} diff --git a/src/soc/ibm/power9/timer.c b/src/soc/ibm/power9/timer.c new file mode 100644 index 0000000000..9a283e3f76 --- /dev/null +++ b/src/soc/ibm/power9/timer.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void init_timer(void) +{ + /* No need to do anything here as long as udelay() is implemented via monolitic timer */ +} -- cgit v1.2.3