From 5ed4d63fe12b9dc744a15a76c136132cc42308db Mon Sep 17 00:00:00 2001
From: Nicolas Boichat <drinkcat@chromium.org>
Date: Tue, 19 May 2020 14:24:33 +0800
Subject: mb/google/asurada: enable SPI devices

Configure and initialize EC and TPM on Asurada.

BUG=none
TEST=boot asurada

Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/asurada/Kconfig     | 4 ++--
 src/mainboard/google/asurada/bootblock.c | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig
index 894d5666b5..7c93815ae8 100644
--- a/src/mainboard/google/asurada/Kconfig
+++ b/src/mainboard/google/asurada/Kconfig
@@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER
 
 config DRIVER_TPM_SPI_BUS
 	hex
-	default 0x0
+	default 0x5
 
 # On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus.
 # The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
@@ -49,6 +49,6 @@ config BOOT_DEVICE_SPI_FLASH_BUS
 
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
-	default 0x2
+	default 0x1
 
 endif
diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c
index 5dcae8c79b..cce14381f6 100644
--- a/src/mainboard/google/asurada/bootblock.c
+++ b/src/mainboard/google/asurada/bootblock.c
@@ -1,7 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <soc/spi.h>
 
 void bootblock_mainboard_init(void)
 {
+	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
+	mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
 }
-- 
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