From 5e0db41602d7e1550d6f669e65dcceb91c291e65 Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Wed, 23 Dec 2020 04:42:26 +0800 Subject: mb/google/zork: adjust the eDP panel power sequence set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight on and vary backlight. BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on dalboz Signed-off-by: Chris Wang Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/zork/variants/vilboz/overridetree.cb | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index ddcaf53d3b..c3afe1372a 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -26,6 +26,18 @@ chip soc/amd/picasso # eDP phy tuning settings register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, + # and "0" as default value + register "edp_pwr_adjust_enable" = "1" + register "pwron_digon_to_de" = "0" + register "pwron_de_to_varybl" = "0" + register "pwrdown_varybloff_to_de" = "0" + register "pwrdown_de_to_digoff" = "0" + register "pwroff_delay" = "0" + register "pwron_varybl_to_blon" = "5" + register "pwrdown_bloff_to_varybloff" = "5" + register "min_allowed_bl_level" = "0" + register "edp_tuningset" = "{ .dp_vs_pemph_level = 0x0, .deemph_6db4 = 0x004b, -- cgit v1.2.3