From 5bd926428eb0972074ec056835eb0f85984846d3 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 6 Jan 2019 16:13:07 +0200 Subject: usbdebug: Sanity check PCI EHCI location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If requested EHCI function is not on bus 0, we would need to open MMIO windows and configuration register space for the connected upstream PCI bridge for it to work. We don't plan to do so. Change-Id: I7c1c60f9d9890dedfedc9d977faf5152ba362692 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30692 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/drivers/usb/pci_ehci.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index e0f88ec098..c05129163e 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -34,6 +34,10 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) { pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + /* We only support controllers on bus 0. */ + if (PCI_DEV2SEGBUS(dbg_dev) != 0) + return -1; + #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = dbg_dev; #else -- cgit v1.2.3