From 5bceca1c530cbb8412828a937085e9afc035e212 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 1 Sep 2017 22:48:07 +0200 Subject: nb/intel/common: Write MRC cache at exit of BS_DEV_INIT We set the SPI lockdown in BS_POST_DEVICE (dev_finalize()) on many plat- forms now. The SPI controller is initialized at start of BS_DEV_INIT (dev_initialize()). The SPI lockdown usually shouldn't be a problem but the SPI driver imple- mentation lacks full support for the locked interface. Also, some options exist to lock all flash regions read-only until the next reboot. Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/21326 Tested-by: build bot (Jenkins) Reviewed-by: Nicola Corna Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Reviewed-by: Bill XIE --- src/northbridge/intel/common/mrc_cache.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c index 2fc8d96ee5..f692282115 100644 --- a/src/northbridge/intel/common/mrc_cache.c +++ b/src/northbridge/intel/common/mrc_cache.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -162,6 +163,9 @@ static void update_mrc_cache(void *unused) int ret; struct spi_flash flash; + if (acpi_is_wakeup_s3()) + return; + if (!current) { printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); return; @@ -231,7 +235,8 @@ static void update_mrc_cache(void *unused) printk(BIOS_DEBUG, "Successfully wrote MRC cache\n"); } -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); +/* Do it before chipset is locked during BS_POST_DEVICE. */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, update_mrc_cache, NULL); struct mrc_data_container *find_current_mrc_cache(void) { -- cgit v1.2.3