From 5af2deae92abd1258a752f29fbe48c91458706c2 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 31 Oct 2017 11:53:13 +0100 Subject: nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width The bus width has to be encoded where the lower 3 bits are the bus width in multiple of 8 and the following two bits give the error checking bits in multiple of 8. Hardcode to 64 bit as done on haswell. TODO: Make it dynamic once there's ECC support. Change-Id: I3b83a098205455b1c820d0436c6984938f261466 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/22261 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/sandybridge/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b31f28042a..e566057d85 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -113,7 +113,7 @@ static void fill_smbios17(ramctr_timing *ctrl) info->dimm[channel][slot].part_number, 16); dimm->mod_id = info->dimm[channel][slot].manufacturer_id; dimm->mod_type = info->dimm[channel][slot].dimm_type; - dimm->bus_width = info->dimm[channel][slot].width; + dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only mem_info->dimm_cnt++; } } -- cgit v1.2.3