From 5a13d6617cde9c676ce72b31c79a272c70449d29 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 17 Nov 2021 15:26:24 +0530 Subject: soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT This patch uses `clrsetbits32` helper function to set thermal device Low Temp Threshold (LTT) value. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp with this change. Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/59310 Reviewed-by: Felix Singer Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/thermal/thermal.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src') diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 4a2d8d88a8..6106c49639 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -40,7 +40,6 @@ static uint32_t pch_get_ltt_value(void) /* Enable thermal sensor power management */ void pch_thermal_configuration(void) { - uint16_t reg16; uintptr_t thermalbar; uintptr_t thermalbar_pm; const struct device *dev; @@ -65,9 +64,5 @@ void pch_thermal_configuration(void) thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ - reg16 = read16((uint16_t *)thermalbar_pm); - reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK; - /* Low Temp Threshold (LTT) */ - reg16 |= pch_get_ltt_value(); - write16((uint16_t *)thermalbar_pm, reg16); + clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value()); } -- cgit v1.2.3