From 57760e3cdf19b1339f936bd89f082dc2701397ba Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Tue, 17 Oct 2017 09:04:58 +0200 Subject: pcengines/apu2: Add timestamps to romstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change adds timestamps to romstage in order to keep PC Engines apu2 platform in active codebase. Change-Id: Ie0286d4982623da9d035c47df6077edaf51e5110 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/22071 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel --- src/mainboard/pcengines/apu2/romstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src') diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 1ccf7c4e36..9eb9e817d0 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -56,6 +57,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + post_code(0x30); early_lpc_init(); @@ -82,8 +86,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); + timestamp_add_now(TS_BEFORE_INITRAM); + post_code(0x40); AGESAWRAPPER(amdinitpost); + + /* FIXME: Detect if TSC frequency changed during raminit? */ + timestamp_rescale_table(1, 4); + + timestamp_add_now(TS_AFTER_INITRAM); } void agesa_postcar(struct sysinfo *cb) -- cgit v1.2.3