From 563424e986edc1027d49c0efd151118a2e687c86 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 14 May 2020 14:52:14 -0700 Subject: Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports" This reverts commit 2412924bc7646fc22b2cb1b9108413fa3e849082. Reason for revert: Resource allocator patches need to be reverted until the AMD chipsets can be fixed to handle the resource allocation flow correctly. BUG=b:149186922 Change-Id: Iea6db8cc0cb5a0e81d176ed3199c91dcd02d1859 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41411 Reviewed-by: Angel Pons Reviewed-by: Mike Banon Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 68759636a0..de77633153 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -15,7 +15,6 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 - select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE if BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -67,20 +66,6 @@ config MAX_CPUS int default 8 -# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569) -# Revision 0.7.6 Section 7.2.5.1.5 -config PCIEXP_HOTPLUG_BUSES - int - default 42 - -config PCIEXP_HOTPLUG_MEM - hex - default 0xc200000 # 194 MiB - -config PCIEXP_HOTPLUG_PREFETCH_MEM - hex - default 0x1c000000 # 448 MiB - config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) -- cgit v1.2.3