From 55e265ea39506d2b340e5c6d621b42ac61d33702 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 9 Sep 2024 12:43:02 +0100 Subject: mb/starlabs/starbook/tgl: Alphabetize and group FSP UPDs Change-Id: I6bab0a316ea7d0f7dfbf599e5c08517cee559635 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/84268 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Matt DeVillier --- src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 11441621c2..3f7762120e 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -1,7 +1,10 @@ chip soc/intel/tigerlake -# CPU - # Enable Enhanced Intel SpeedStep + # FSP UPDs register "eist_enable" = "true" + register "enable_c6dram" = "1" + register "CnviBtCore" = "true" + register "CnviBtAudioOffload" = "1" + register "SaGv" = "SaGv_Enabled" # Graphics # Not used but timings left for reference @@ -14,13 +17,6 @@ chip soc/intel/tigerlake # .backlight_pwm_hz = 200, // PWM # }" - # FSP Memory - register "CnviBtCore" = "true" - register "CnviBtAudioOffload" = "1" - register "enable_c6dram" = "1" - register "SaGv" = "SaGv_Enabled" - - # FSP Silicon # Serial I/O register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- cgit v1.2.3