From 54e9894353ec2c6e635bead94a94953db069d49d Mon Sep 17 00:00:00 2001 From: Matt Delco Date: Mon, 9 Mar 2020 12:41:09 -0700 Subject: soc/intel: fix eist enabling There was a bug like this for skylake that seems to have been copied to other SoCs. Signed-off-by: Matt Delco Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/cpu.c | 3 ++- src/soc/intel/icelake/cpu.c | 3 ++- src/soc/intel/skylake/cpu.c | 9 +++------ src/soc/intel/tigerlake/cpu.c | 3 ++- 4 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f01b499108..3ba0562980 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -263,9 +263,10 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index e058442585..91282d8a66 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -71,9 +71,10 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index f5273f6fc7..d7da56eaf7 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -291,14 +291,11 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - - if (conf->eist_enable) - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - else - msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ - wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); + /* Disable Thermal interrupts */ msr.lo = 0; msr.hi = 0; diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 5f4f081818..cfbfdb3ea4 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -77,9 +77,10 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; -- cgit v1.2.3