From 54a2a0ad45177e1d09cc007fe3db2f6b41a4924c Mon Sep 17 00:00:00 2001 From: Ryan Chuang Date: Tue, 6 Jul 2021 17:14:29 +0800 Subject: vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability Signed-off-by: Ryan Chuang Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56105 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index 71415d2127..b761473955 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -33,7 +33,7 @@ U8 gHQA_Test_Freq_Vcore_Level = 0; // 0: only 1 freq , others are multi freq u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733 DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { - {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION {LP4_DDR400 /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF, OPEN_LOOP_MODE}, -- cgit v1.2.3