From 546953c0c553465761705fb0747964c08d634461 Mon Sep 17 00:00:00 2001
From: Patrick Georgi <pgeorgi@google.com>
Date: Sat, 29 Nov 2014 10:38:17 +0100
Subject: Replace hlt with halt()

There were instances of unneeded arch/hlt.h includes,
various hlt() calls that weren't supposed to exit (but
might have) and various forms of endless loops around
hlt() calls.

All these are sorted out now: unnecessary includes are
dropped, hlt() is uniformly replaced with halt() (except
in assembly, obviously).

Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7608
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/arch/arm/armv4/bootblock_simple.c               |  4 ++--
 src/arch/arm/armv7/bootblock_simple.c               |  4 ++--
 src/arch/arm64/armv8/bootblock_simple.c             |  4 ++--
 src/arch/x86/init/bootblock_normal.c                |  3 ++-
 src/arch/x86/init/bootblock_simple.c                |  3 ++-
 src/cpu/intel/haswell/bootblock.c                   |  9 +++------
 src/cpu/intel/model_2065x/bootblock.c               |  3 ++-
 src/cpu/intel/model_206ax/bootblock.c               |  3 ++-
 src/ec/google/chromeec/ec.c                         |  6 +++---
 src/mainboard/a-trend/atc-6220/romstage.c           |  1 -
 src/mainboard/a-trend/atc-6240/romstage.c           |  1 -
 src/mainboard/aaeon/pfm-540i_revb/romstage.c        |  1 -
 src/mainboard/abit/be6-ii_v2_0/romstage.c           |  1 -
 src/mainboard/advantech/pcm-5820/romstage.c         |  1 -
 src/mainboard/amd/db800/romstage.c                  |  1 -
 src/mainboard/amd/norwich/romstage.c                |  1 -
 src/mainboard/amd/rumba/romstage.c                  |  1 -
 src/mainboard/apple/macbook21/romstage.c            |  4 ++--
 src/mainboard/artecgroup/dbe61/romstage.c           |  1 -
 src/mainboard/asi/mb_5blgp/romstage.c               |  1 -
 src/mainboard/asi/mb_5blmp/romstage.c               |  1 -
 src/mainboard/asus/mew-am/romstage.c                |  1 -
 src/mainboard/asus/mew-vm/romstage.c                |  1 -
 src/mainboard/asus/p2b-d/romstage.c                 |  1 -
 src/mainboard/asus/p2b-ds/romstage.c                |  1 -
 src/mainboard/asus/p2b-f/romstage.c                 |  1 -
 src/mainboard/asus/p2b-ls/romstage.c                |  1 -
 src/mainboard/asus/p2b/romstage.c                   |  1 -
 src/mainboard/asus/p3b-f/romstage.c                 |  1 -
 src/mainboard/axus/tc320/romstage.c                 |  1 -
 src/mainboard/azza/pt-6ibd/romstage.c               |  1 -
 src/mainboard/bachmann/ot200/romstage.c             |  1 -
 src/mainboard/bcom/winnet100/romstage.c             |  1 -
 src/mainboard/bcom/winnetp680/romstage.c            |  1 -
 src/mainboard/bifferos/bifferboard/romstage.c       |  1 -
 src/mainboard/biostar/m6tba/romstage.c              |  1 -
 src/mainboard/compaq/deskpro_en_sff_p600/romstage.c |  1 -
 src/mainboard/digitallogic/adl855pc/romstage.c      |  1 -
 src/mainboard/digitallogic/msm586seg/romstage.c     |  1 -
 src/mainboard/digitallogic/msm800sev/romstage.c     |  1 -
 src/mainboard/eaglelion/5bcm/romstage.c             |  1 -
 src/mainboard/ecs/p6iwp-fe/romstage.c               |  1 -
 src/mainboard/emulation/qemu-i440fx/romstage.c      |  1 -
 src/mainboard/emulation/qemu-q35/romstage.c         |  1 -
 src/mainboard/getac/p470/romstage.c                 |  3 ++-
 src/mainboard/gigabyte/ga-6bxc/romstage.c           |  1 -
 src/mainboard/gigabyte/ga-6bxe/romstage.c           |  1 -
 src/mainboard/hp/e_vectra_p2706t/romstage.c         |  1 -
 src/mainboard/ibase/mb899/romstage.c                |  3 ++-
 src/mainboard/iei/juki-511p/romstage.c              |  1 -
 src/mainboard/iei/nova4899r/romstage.c              |  1 -
 src/mainboard/iei/pcisa-lx-800-r10/romstage.c       |  1 -
 src/mainboard/iei/pm-lx-800-r11/romstage.c          |  1 -
 src/mainboard/iei/pm-lx2-800-r10/romstage.c         |  1 -
 src/mainboard/intel/d810e2cb/romstage.c             |  1 -
 src/mainboard/jetway/j7f2/romstage.c                |  1 -
 src/mainboard/kontron/986lcd-m/romstage.c           |  3 ++-
 src/mainboard/lanner/em8510/romstage.c              |  1 -
 src/mainboard/lenovo/t60/romstage.c                 |  3 ++-
 src/mainboard/lenovo/x60/romstage.c                 |  4 ++--
 src/mainboard/lippert/frontrunner/romstage.c        |  1 -
 src/mainboard/lippert/hurricane-lx/romstage.c       |  1 -
 src/mainboard/lippert/literunner-lx/romstage.c      |  1 -
 src/mainboard/lippert/roadrunner-lx/romstage.c      |  1 -
 src/mainboard/lippert/spacerunner-lx/romstage.c     |  1 -
 src/mainboard/mitac/6513wu/romstage.c               |  1 -
 src/mainboard/msi/ms6119/romstage.c                 |  1 -
 src/mainboard/msi/ms6147/romstage.c                 |  1 -
 src/mainboard/msi/ms6156/romstage.c                 |  1 -
 src/mainboard/msi/ms6178/romstage.c                 |  1 -
 src/mainboard/nec/powermate2000/romstage.c          |  1 -
 src/mainboard/nokia/ip530/romstage.c                |  1 -
 src/mainboard/pcengines/alix1c/romstage.c           |  1 -
 src/mainboard/pcengines/alix2d/romstage.c           |  1 -
 src/mainboard/rca/rm4100/romstage.c                 |  1 -
 src/mainboard/roda/rk886ex/romstage.c               |  3 ++-
 src/mainboard/soyo/sy-6ba-plus-iii/romstage.c       |  1 -
 src/mainboard/technologic/ts5300/romstage.c         |  1 -
 src/mainboard/televideo/tc7020/romstage.c           |  1 -
 src/mainboard/thomson/ip1000/romstage.c             |  1 -
 src/mainboard/traverse/geos/romstage.c              |  1 -
 src/mainboard/tyan/s1846/romstage.c                 |  1 -
 src/mainboard/via/epia-cn/romstage.c                |  1 -
 src/mainboard/via/epia-m/romstage.c                 |  1 -
 src/mainboard/via/epia-m700/romstage.c              |  1 -
 src/mainboard/via/epia-m850/romstage.c              |  1 -
 src/mainboard/via/epia-n/romstage.c                 |  1 -
 src/mainboard/via/epia/romstage.c                   |  1 -
 src/mainboard/via/pc2500e/romstage.c                |  1 -
 src/mainboard/via/vt8454c/romstage.c                |  1 -
 src/mainboard/winent/pl6064/romstage.c              |  1 -
 src/mainboard/wyse/s50/romstage.c                   |  1 -
 src/northbridge/intel/gm45/early_reset.c            |  3 ++-
 src/northbridge/intel/i5000/raminit.c               |  5 +++--
 src/northbridge/intel/i945/early_init.c             |  3 ++-
 src/northbridge/intel/i945/raminit.c                |  5 +++--
 src/northbridge/intel/nehalem/raminit.c             | 20 ++++++--------------
 src/northbridge/intel/sandybridge/raminit.c         |  4 ++--
 src/northbridge/via/vx800/examples/romstage.c       |  1 -
 src/soc/intel/baytrail/smihandler.c                 |  4 ++--
 src/soc/intel/broadwell/bootblock/cpu.c             |  9 +++------
 src/soc/intel/broadwell/me.c                        |  1 -
 src/soc/intel/broadwell/romstage/raminit.c          |  1 -
 src/soc/intel/broadwell/smihandler.c                |  4 ++--
 src/soc/intel/fsp_baytrail/smihandler.c             |  4 ++--
 src/soc/nvidia/tegra124/bootblock.c                 |  1 -
 src/soc/samsung/exynos5250/power.c                  |  4 ++--
 src/soc/samsung/exynos5420/power.c                  |  4 ++--
 src/southbridge/intel/bd82x6x/early_me.c            |  4 ++--
 src/southbridge/intel/bd82x6x/early_me_native.c     |  6 +++---
 src/southbridge/intel/bd82x6x/early_pch_native.c    |  1 -
 src/southbridge/intel/bd82x6x/me.c                  |  4 ++--
 src/southbridge/intel/bd82x6x/me_8.x.c              |  4 ++--
 src/southbridge/intel/bd82x6x/smihandler.c          |  4 ++--
 src/southbridge/intel/fsp_bd82x6x/early_me.c        |  4 ++--
 src/southbridge/intel/fsp_bd82x6x/me.c              |  4 ++--
 src/southbridge/intel/fsp_bd82x6x/me_8.x.c          |  4 ++--
 src/southbridge/intel/fsp_bd82x6x/reset.c           |  1 -
 src/southbridge/intel/fsp_bd82x6x/smihandler.c      |  4 ++--
 src/southbridge/intel/fsp_rangeley/reset.c          |  1 -
 src/southbridge/intel/i82801gx/smihandler.c         |  4 ++--
 src/southbridge/intel/ibexpeak/me.c                 |  1 -
 src/southbridge/intel/ibexpeak/smihandler.c         |  4 ++--
 src/southbridge/intel/lynxpoint/me_9.x.c            |  4 ++--
 src/southbridge/intel/lynxpoint/smihandler.c        |  4 ++--
 125 files changed, 92 insertions(+), 177 deletions(-)

(limited to 'src')

diff --git a/src/arch/arm/armv4/bootblock_simple.c b/src/arch/arm/armv4/bootblock_simple.c
index 80401b3951..207279b2f6 100644
--- a/src/arch/arm/armv4/bootblock_simple.c
+++ b/src/arch/arm/armv4/bootblock_simple.c
@@ -20,11 +20,11 @@
  */
 
 #include <arch/exception.h>
-#include <arch/hlt.h>
 #include <arch/stages.h>
 #include <bootblock_common.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <halt.h>
 
 void main(void)
 {
@@ -42,5 +42,5 @@ void main(void)
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
 
 	if (entry) stage_exit(entry);
-	hlt();
+	halt();
 }
diff --git a/src/arch/arm/armv7/bootblock_simple.c b/src/arch/arm/armv7/bootblock_simple.c
index 248ea4e2b5..aad63b67f9 100644
--- a/src/arch/arm/armv7/bootblock_simple.c
+++ b/src/arch/arm/armv7/bootblock_simple.c
@@ -21,11 +21,11 @@
 
 #include <arch/cache.h>
 #include <arch/exception.h>
-#include <arch/hlt.h>
 #include <arch/stages.h>
 #include <bootblock_common.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <halt.h>
 #include <smp/node.h>
 
 void main(void)
@@ -44,5 +44,5 @@ void main(void)
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
 
 	if (entry) stage_exit(entry);
-	hlt();
+	halt();
 }
diff --git a/src/arch/arm64/armv8/bootblock_simple.c b/src/arch/arm64/armv8/bootblock_simple.c
index d8339d1f76..7948f2f717 100644
--- a/src/arch/arm64/armv8/bootblock_simple.c
+++ b/src/arch/arm64/armv8/bootblock_simple.c
@@ -21,11 +21,11 @@
 
 #include <bootblock_common.h>
 #include <arch/cache.h>
-#include <arch/hlt.h>
 #include <arch/stages.h>
 #include <arch/exception.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <halt.h>
 
 static int boot_cpu(void)
 {
@@ -69,5 +69,5 @@ void main(void)
 	printk(BIOS_SPEW, "stage_name %s, entry %p\n", stage_name, entry);
 
 	if (entry) stage_exit(entry);
-	hlt();
+	halt();
 }
diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c
index 218d456ad3..bde2535ba6 100644
--- a/src/arch/x86/init/bootblock_normal.c
+++ b/src/arch/x86/init/bootblock_normal.c
@@ -1,6 +1,7 @@
 #include <smp/node.h>
 #include <bootblock_common.h>
 #include <pc80/mc146818rtc.h>
+#include <halt.h>
 
 static const char *get_fallback(const char *stagelist) {
 	while (*stagelist) stagelist++;
@@ -47,5 +48,5 @@ static void main(unsigned long bist)
 	if (entry) call(entry, bist);
 
 	/* duh. we're stuck */
-	asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
+	halt();
 }
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c
index 179595a727..adeecf7ba6 100644
--- a/src/arch/x86/init/bootblock_simple.c
+++ b/src/arch/x86/init/bootblock_simple.c
@@ -1,5 +1,6 @@
 #include <smp/node.h>
 #include <bootblock_common.h>
+#include <halt.h>
 
 static void main(unsigned long bist)
 {
@@ -18,5 +19,5 @@ static void main(unsigned long bist)
 	unsigned long entry;
 	entry = findstage(target1);
 	if (entry) call(entry, bist);
-	asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
+	halt();
 }
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index 4857f23e69..366c56b179 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -23,6 +23,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
+#include <halt.h>
 
 #include <cpu/intel/microcode/microcode.c>
 #include "haswell.h"
@@ -106,9 +107,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, 0xcf9);
 	outb(0x6, 0xcf9);
-	while (1) {
-		asm("hlt");
-	}
+	halt();
 }
 
 static void check_for_clean_reset(void)
@@ -122,9 +121,7 @@ static void check_for_clean_reset(void)
 	if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) {
 		outb(0x0, 0xcf9);
 		outb(0x6, 0xcf9);
-		while (1) {
-			asm("hlt");
-		}
+		halt();
 	}
 }
 
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index fa8e137c00..23fb02ab88 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -23,6 +23,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
+#include <halt.h>
 
 #include <cpu/intel/microcode/microcode.c>
 
@@ -109,7 +110,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, 0xcf9);
 	outb(0x6, 0xcf9);
-	asm("hlt");
+	halt();
 }
 
 static void bootblock_cpu_init(void)
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 49c4012eee..d6fa2e7521 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -23,6 +23,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
+#include <halt.h>
 
 #include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"
@@ -110,7 +111,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, 0xcf9);
 	outb(0x6, 0xcf9);
-	asm("hlt");
+	halt();
 }
 
 static void bootblock_cpu_init(void)
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 24f9693735..e5a9e9a54a 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -23,7 +23,7 @@
 #include <bootmode.h>
 #include <arch/io.h>
 #include <delay.h>
-#include <arch/hlt.h>
+#include <halt.h>
 #include <reset.h>
 #include <elog.h>
 #include <stdlib.h>
@@ -125,7 +125,7 @@ void google_chromeec_check_ec_image(int expected_type)
 		google_chromeec_command(&cec_cmd);
 		udelay(1000);
 		hard_reset();
-		hlt();
+		halt();
 	}
 }
 
@@ -447,7 +447,7 @@ void google_chromeec_init(void)
 		google_chromeec_command(&cec_cmd);
 		udelay(1000);
 		hard_reset();
-		hlt();
+		halt();
 	}
 
 }
diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c
index 70bc5d8be2..16c9286e89 100644
--- a/src/mainboard/a-trend/atc-6220/romstage.c
+++ b/src/mainboard/a-trend/atc-6220/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c
index 392f40fd7a..8485285abd 100644
--- a/src/mainboard/a-trend/atc-6240/romstage.c
+++ b/src/mainboard/a-trend/atc-6240/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
index c4bf462b06..a664e9e06f 100644
--- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c
+++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
@@ -26,7 +26,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c
index 41a09daab3..63dfec6f97 100644
--- a/src/mainboard/abit/be6-ii_v2_0/romstage.c
+++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c
index a6b856e4d3..77cb154172 100644
--- a/src/mainboard/advantech/pcm-5820/romstage.c
+++ b/src/mainboard/advantech/pcm-5820/romstage.c
@@ -21,7 +21,6 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 3df26c66f6..63e9275141 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 1b8a303f03..2c8293742f 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index 2d43fff9f7..248baa0d3a 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 8d3fc67252..39a8e466b0 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -35,6 +35,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -313,8 +314,7 @@ void main(unsigned long bist)
 		printk(BIOS_DEBUG,
 		       "Soft reset detected, rebooting properly.\n");
 		outb(0x6, 0xcf9);
-		while (1)
-			asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 343351f6c4..63f89f1d6c 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c
index 43c5cf79f3..ac76f34e88 100644
--- a/src/mainboard/asi/mb_5blgp/romstage.c
+++ b/src/mainboard/asi/mb_5blgp/romstage.c
@@ -21,7 +21,6 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c
index 1fb3378132..96e884d6dd 100644
--- a/src/mainboard/asi/mb_5blmp/romstage.c
+++ b/src/mainboard/asi/mb_5blmp/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/early_serial.c"
diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c
index 7a79e8518d..15d7791ca8 100644
--- a/src/mainboard/asus/mew-am/romstage.c
+++ b/src/mainboard/asus/mew-am/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801ax/i82801ax.h"
 #include "northbridge/intel/i82810/raminit.h"
diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c
index 04bbd869e8..d2d418606b 100644
--- a/src/mainboard/asus/mew-vm/romstage.c
+++ b/src/mainboard/asus/mew-vm/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "superio/smsc/lpc47b272/early_serial.c"
diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c
index d41afc8890..83073116ff 100644
--- a/src/mainboard/asus/p2b-d/romstage.c
+++ b/src/mainboard/asus/p2b-d/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c
index 494a3f030d..56992c52d0 100644
--- a/src/mainboard/asus/p2b-ds/romstage.c
+++ b/src/mainboard/asus/p2b-ds/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c
index 1b905e45c3..7cf009948f 100644
--- a/src/mainboard/asus/p2b-f/romstage.c
+++ b/src/mainboard/asus/p2b-f/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c
index 09b9a4e00a..fb90a68a6a 100644
--- a/src/mainboard/asus/p2b-ls/romstage.c
+++ b/src/mainboard/asus/p2b-ls/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c
index 70bc5d8be2..16c9286e89 100644
--- a/src/mainboard/asus/p2b/romstage.c
+++ b/src/mainboard/asus/p2b/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index 78c76292b8..2655fc7a22 100644
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c
index 15362e3b28..158a45fbde 100644
--- a/src/mainboard/axus/tc320/romstage.c
+++ b/src/mainboard/axus/tc320/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/early_serial.c"
diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c
index b31be70b0d..804e34c793 100644
--- a/src/mainboard/azza/pt-6ibd/romstage.c
+++ b/src/mainboard/azza/pt-6ibd/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c
index 849479c828..7951a57700 100644
--- a/src/mainboard/bachmann/ot200/romstage.c
+++ b/src/mainboard/bachmann/ot200/romstage.c
@@ -25,7 +25,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c
index 15362e3b28..158a45fbde 100644
--- a/src/mainboard/bcom/winnet100/romstage.c
+++ b/src/mainboard/bcom/winnet100/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/early_serial.c"
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 898ad1a402..170a90997f 100644
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c
index dd2553e9ba..574e9a6caf 100644
--- a/src/mainboard/bifferos/bifferboard/romstage.c
+++ b/src/mainboard/bifferos/bifferboard/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c
index 921aa52c63..a91318dfaf 100644
--- a/src/mainboard/biostar/m6tba/romstage.c
+++ b/src/mainboard/biostar/m6tba/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
index 70f820aeca..feccfb7efe 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index 093c60be6b..ce8ef13a80 100644
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <lib.h>
 #include "drivers/pc80/udelay_io.c"
diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c
index ab944a4233..2cc0ab5864 100644
--- a/src/mainboard/digitallogic/msm586seg/romstage.c
+++ b/src/mainboard/digitallogic/msm586seg/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 8bfe8e581c..4df217f236 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -3,7 +3,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c
index 28ddcc5668..f2476106c4 100644
--- a/src/mainboard/eaglelion/5bcm/romstage.c
+++ b/src/mainboard/eaglelion/5bcm/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "superio/nsc/pc97317/early_serial.c"
diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c
index 9d5f2cd0cf..0ffcfa5ede 100644
--- a/src/mainboard/ecs/p6iwp-fe/romstage.c
+++ b/src/mainboard/ecs/p6iwp-fe/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801ax/i82801ax.h"
 #include "northbridge/intel/i82810/raminit.h"
diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c
index 6c17645cdb..c617a0a3fe 100644
--- a/src/mainboard/emulation/qemu-i440fx/romstage.c
+++ b/src/mainboard/emulation/qemu-i440fx/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
index dd86701cb0..658051c0c8 100644
--- a/src/mainboard/emulation/qemu-q35/romstage.c
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index ccfb076525..7b60ae5fab 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -31,6 +31,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -292,7 +293,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c
index e0a248b441..9e465dd071 100644
--- a/src/mainboard/gigabyte/ga-6bxc/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
index 5d69510675..369a23f0f3 100644
--- a/src/mainboard/gigabyte/ga-6bxe/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c
index c34801e121..baa19954f8 100644
--- a/src/mainboard/hp/e_vectra_p2706t/romstage.c
+++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 /* TODO: It's a PC87364 actually! */
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 2a81921152..38e862007f 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
@@ -243,7 +244,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c
index 1b8e952fc7..a58407a524 100644
--- a/src/mainboard/iei/juki-511p/romstage.c
+++ b/src/mainboard/iei/juki-511p/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977f/early_serial.c"
 #include "southbridge/amd/cs5530/enable_rom.c"
diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c
index 2b6caf3a17..a146d8e1f7 100644
--- a/src/mainboard/iei/nova4899r/romstage.c
+++ b/src/mainboard/iei/nova4899r/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977tf/early_serial.c"
 #include "southbridge/amd/cs5530/enable_rom.c"
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index 9f4223217c..b11f5cb7ca 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c
index ac68b1d31e..a8e860d1ae 100644
--- a/src/mainboard/iei/pm-lx-800-r11/romstage.c
+++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c
@@ -22,7 +22,6 @@
 #include <stdlib.h>
 #include <spd.h>
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <console/console.h>
diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c
index a83bf7ecc0..04e7bd0ad8 100644
--- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c
+++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c
@@ -23,7 +23,6 @@
 #include <stdlib.h>
 #include <spd.h>
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <console/console.h>
diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c
index 8b74b17d9f..a6958eeaae 100644
--- a/src/mainboard/intel/d810e2cb/romstage.c
+++ b/src/mainboard/intel/d810e2cb/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801bx/i82801bx.h"
 #include "northbridge/intel/i82810/raminit.h"
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c
index a9c71c3062..a66467b8f1 100644
--- a/src/mainboard/jetway/j7f2/romstage.c
+++ b/src/mainboard/jetway/j7f2/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 2c89e6cbc7..dc7da996e0 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -32,6 +32,7 @@
 #include "option_table.h"
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include <superio/winbond/w83627thg/w83627thg.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
@@ -354,7 +355,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index c51ee35098..c1a02f4f0d 100644
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <lib.h>
 #include <spd.h>
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index f0ebcbc2a7..350c2dead3 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -35,6 +35,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -253,7 +254,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 1310b3377e..4596a1a2d2 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -35,6 +35,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -253,8 +254,7 @@ void main(unsigned long bist)
 		printk(BIOS_DEBUG,
 		       "Soft reset detected, rebooting properly.\n");
 		outb(0x6, 0xcf9);
-		while (1)
-			asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index 81642a11d2..3be4eb3d1c 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -3,7 +3,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index d8e9cd9589..416a8fb9fa 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -26,7 +26,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 68393323ea..8b48640306 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -27,7 +27,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index ef3f7d2d08..4d8a6fd443 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -26,7 +26,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index f397e37d74..3c25c084d9 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -27,7 +27,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c
index e29423eb45..2710082bb0 100644
--- a/src/mainboard/mitac/6513wu/romstage.c
+++ b/src/mainboard/mitac/6513wu/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801ax/i82801ax.h"
 #include "northbridge/intel/i82810/raminit.h"
diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c
index be273f3601..fb30e49fed 100644
--- a/src/mainboard/msi/ms6119/romstage.c
+++ b/src/mainboard/msi/ms6119/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c
index c3a755749e..916f0e9aa2 100644
--- a/src/mainboard/msi/ms6147/romstage.c
+++ b/src/mainboard/msi/ms6147/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c
index ff888bcbea..e8dbb02993 100644
--- a/src/mainboard/msi/ms6156/romstage.c
+++ b/src/mainboard/msi/ms6156/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c
index ae789902e2..66a9c9bf74 100644
--- a/src/mainboard/msi/ms6178/romstage.c
+++ b/src/mainboard/msi/ms6178/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <superio/winbond/common/winbond.h>
diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c
index d4a2d8f7af..6bbfc1a0bf 100644
--- a/src/mainboard/nec/powermate2000/romstage.c
+++ b/src/mainboard/nec/powermate2000/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <superio/smsc/smscsuperio/smscsuperio.h>
diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c
index 5c878675c1..3c5511b48b 100644
--- a/src/mainboard/nokia/ip530/romstage.c
+++ b/src/mainboard/nokia/ip530/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 4f80550713..f4bbc317fb 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 52c5310c1a..1316d5ec9d 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index af91bde514..500416ae1e 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include "drivers/pc80/udelay_io.c"
 #include <console/console.h>
 #include <lib.h>
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 071fa2a7b2..c9ec4f152d 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -276,7 +277,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
index 82ac56fa42..531e2236f2 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c
index 5d33baee25..9cafc64f37 100644
--- a/src/mainboard/technologic/ts5300/romstage.c
+++ b/src/mainboard/technologic/ts5300/romstage.c
@@ -8,7 +8,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c
index 15362e3b28..158a45fbde 100644
--- a/src/mainboard/televideo/tc7020/romstage.c
+++ b/src/mainboard/televideo/tc7020/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/early_serial.c"
diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
index bb8d15cc7a..ede49f7ac1 100644
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ b/src/mainboard/thomson/ip1000/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include "drivers/pc80/udelay_io.c"
 #include <console/console.h>
 #include <lib.h>
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index b3358b5f5d..76e4a5c883 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c
index 0c81e8e890..10af34da25 100644
--- a/src/mainboard/tyan/s1846/romstage.c
+++ b/src/mainboard/tyan/s1846/romstage.c
@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 20f99cb624..8a0d384cad 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "northbridge/via/cn700/raminit.h"
diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c
index 3f2a0c4084..f63b6a855c 100644
--- a/src/mainboard/via/epia-m/romstage.c
+++ b/src/mainboard/via/epia-m/romstage.c
@@ -3,7 +3,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "northbridge/via/vt8623/raminit.h"
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index b00ece1a3a..c9b1e8b1c0 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -30,7 +30,6 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "northbridge/via/vx800/vx800.h"
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 7b62d86105..899c5a6be4 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index 2ede8d87cb..0de7556579 100644
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/via/cn400/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c
index 1d312d7267..5e209409f4 100644
--- a/src/mainboard/via/epia/romstage.c
+++ b/src/mainboard/via/epia/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "northbridge/via/vt8601/raminit.h"
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index 0b1aeb4761..57e5cd09a3 100644
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index f6d58c8e70..bb2d8789cd 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "northbridge/via/cx700/raminit.h"
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 47ea7222f5..56b13296a1 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index b9de16c184..6283c9c0de 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index fccb97f612..babb99478d 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -21,6 +21,7 @@
 
 #include <types.h>
 #include <arch/io.h>
+#include <halt.h>
 #include "gm45.h"
 
 void gm45_early_reset(void/*const timings_t *const timings*/)
@@ -69,5 +70,5 @@ void gm45_early_reset(void/*const timings_t *const timings*/)
 	/* Perform system reset through CF9 interface. */
 	outb(0x02, 0xcf9); /* Set system reset bit. */
 	outb(0x06, 0xcf9); /* Set cpu reset bit, too. */
-	while (1) asm("hlt");
+	halt();
 }
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index 9c694c7d28..539400293b 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -26,6 +26,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
 #include <console/console.h>
+#include <halt.h>
 #include <spd.h>
 #include <types.h>
 #include <string.h>
@@ -1522,7 +1523,7 @@ static void i5000_try_restart(const char *msg)
 	printk(BIOS_INFO, "%s", msg);
 	i5000_dump_error_registers();
 	outb(0x06, 0xcf9);
-	for(;;) asm volatile("hlt");
+	halt();
 }
 
 static void i5000_pam_setup(void)
@@ -1624,7 +1625,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
 		pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq);
 		/* FSB:FBD mapping changed, needs hard reset */
 		outb(0x06, 0xcf9);
-		for(;;) asm volatile("hlt");
+		halt();
 	}
 	return 0;
 }
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index f639aef146..aaa17e503b 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -23,6 +23,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <cbmem.h>
+#include <halt.h>
 #include <string.h>
 #include "i945.h"
 
@@ -512,7 +513,7 @@ static void i945_setup_dmi_rcrb(void)
 			reg32 |= (3 << 0);
 			DMIBAR32(0x224) = reg32;
 			outb(0x06, 0xcf9);
-			for (;;) asm("hlt");	/* wait for reset */
+			halt(); /* wait for reset */
 		}
 	}
 }
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index e823bab455..e9b6e3ffed 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -24,6 +24,7 @@
 #include <spd.h>
 #include <string.h>
 #include <arch/io.h>
+#include <halt.h>
 #include <lib.h>
 #include "raminit.h"
 #include "i945.h"
@@ -281,7 +282,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
 			printk(BIOS_DEBUG, "Reset required.\n");
 			outb(0x00, 0xcf9);
 			outb(0x0e, 0xcf9);
-			for (;;) asm("hlt"); /* Wait for reset! */
+			halt(); /* Wait for reset! */
 		}
 	}
 
@@ -311,7 +312,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
 		printk(BIOS_DEBUG, "Reset required.\n");
 		outb(0x00, 0xcf9);
 		outb(0x0e, 0xcf9);
-		for (;;) asm("hlt"); /* Wait for reset! */
+		halt(); /* Wait for reset! */
 	}
 }
 
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 74ddb4b3ff..fb82484444 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -28,7 +28,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cpu/x86/msr.h>
 #include <cbmem.h>
@@ -38,6 +37,7 @@
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
 #include <arch/cpu.h>
+#include <halt.h>
 #include <spd.h>
 #include "raminit.h"
 #include <timestamp.h>
@@ -3805,9 +3805,7 @@ void chipset_init(const int s3resume)
 		write_mchbar8(0x2ca8, 0);
 		outb(0x6, 0xcf9);
 #if REAL
-		while (1) {
-			asm volatile ("hlt");
-		}
+		halt();
 #else
 		printf("CP5\n");
 		exit(0);
@@ -4041,9 +4039,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 			       "Interrupted RAM init, reset required.\n");
 			outb(0x6, 0xcf9);
 #if REAL
-			while (1) {
-				asm volatile ("hlt");
-			}
+			halt();
 #endif
 		}
 	}
@@ -4407,9 +4403,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 		write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4);
 		write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10);
 #if REAL
-		while (1) {
-			asm volatile ("hlt");
-		}
+		halt();
 #else
 		printf("CP5\n");
 		exit(0);
@@ -4510,9 +4504,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 			outb(0xe, 0xcf9);
 
 #if REAL
-			while (1) {
-				asm volatile ("hlt");
-			}
+			halt();
 #else
 			printf("CP5\n");
 			exit(0);
@@ -4990,7 +4982,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0xe, 0xcf9);
-		hlt();
+		halt();
 	}
 #endif
 }
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index d2ae4b039e..f6c92dbd11 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -21,7 +21,6 @@
 #include <console/usb.h>
 #include <bootmode.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
@@ -29,6 +28,7 @@
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
+#include <halt.h>
 #include "raminit.h"
 #include "pei_data.h"
 #include "sandybridge.h"
@@ -239,7 +239,7 @@ void sdram_initialize(struct pei_data *pei_data)
 	if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
 		printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Pass console handler in pei_data */
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 2ab3e64659..c96511e2c9 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/vx800/vx800.h"
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 22b60c42d3..62de9fad4a 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -19,13 +19,13 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_def.h>
 #include <elog.h>
+#include <halt.h>
 
 #include <baytrail/pci_devs.h>
 #include <baytrail/pmc.h>
@@ -161,7 +161,7 @@ static void southbridge_smi_sleep(void)
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 
 	/* In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake
diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c
index 11f1833fd0..da7b99df62 100644
--- a/src/soc/intel/broadwell/bootblock/cpu.c
+++ b/src/soc/intel/broadwell/bootblock/cpu.c
@@ -23,6 +23,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
+#include <halt.h>
 #include <cpu/intel/microcode/microcode.c>
 #include <broadwell/rcba.h>
 #include <broadwell/msr.h>
@@ -99,9 +100,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, 0xcf9);
 	outb(0x6, 0xcf9);
-	while (1) {
-		asm("hlt");
-	}
+	halt();
 }
 
 static void check_for_clean_reset(void)
@@ -115,9 +114,7 @@ static void check_for_clean_reset(void)
 	if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) {
 		outb(0x0, 0xcf9);
 		outb(0x6, 0xcf9);
-		while (1) {
-			asm("hlt");
-		}
+		halt();
 	}
 }
 
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 15bcc348cd..2bdb1ed935 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -26,7 +26,6 @@
  */
 
 #include <arch/acpi.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index a5f688ea69..d4ebc08da8 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -18,7 +18,6 @@
  */
 
 #include <arch/cbfs.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cbfs.h>
 #include <cbmem.h>
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 6acd07cdc0..85a4f47e44 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -20,7 +20,6 @@
 
 #include <delay.h>
 #include <types.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
@@ -28,6 +27,7 @@
 #include <cpu/x86/smm.h>
 #include <spi-generic.h>
 #include <elog.h>
+#include <halt.h>
 #include <pc80/mc146818rtc.h>
 #include <broadwell/lpc.h>
 #include <broadwell/nvs.h>
@@ -197,7 +197,7 @@ static void southbridge_smi_sleep(void)
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 
 	/*
 	 * In most sleep states, the code flow of this function ends at
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index 2225964268..234a34f4e3 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -19,13 +19,13 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_def.h>
 #include <elog.h>
+#include <halt.h>
 
 #include <baytrail/pci_devs.h>
 #include <baytrail/pmc.h>
@@ -161,7 +161,7 @@ static void southbridge_smi_sleep(void)
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 
 	/* In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index 22024af90b..6acd5ad4d6 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -18,7 +18,6 @@
  */
 
 #include <arch/exception.h>
-#include <arch/hlt.h>
 #include <bootblock_common.h>
 #include <cbfs.h>
 #include <console/console.h>
diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c
index c9d620a958..fb45dc0dd4 100644
--- a/src/soc/samsung/exynos5250/power.c
+++ b/src/soc/samsung/exynos5250/power.c
@@ -20,8 +20,8 @@
 /* Power setup code for EXYNOS5 */
 
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <console/console.h>
+#include <halt.h>
 #include "power.h"
 
 static void ps_hold_setup(void)
@@ -45,7 +45,7 @@ void power_shutdown(void)
 	clrbits_le32(&exynos_power->ps_hold_ctrl,
 		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 
-	hlt();
+	halt();
 }
 
 void power_enable_dp_phy(void)
diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c
index ecaf208c9c..a7e5262e12 100644
--- a/src/soc/samsung/exynos5420/power.c
+++ b/src/soc/samsung/exynos5420/power.c
@@ -20,8 +20,8 @@
 /* Power setup code for EXYNOS5 */
 
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <console/console.h>
+#include <halt.h>
 #include "dmc.h"
 #include "power.h"
 #include "setup.h"
@@ -47,7 +47,7 @@ void power_shutdown(void)
 	clrbits_le32(&exynos_power->ps_hold_ctrl,
 		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 
-	hlt();
+	halt();
 }
 
 void power_enable_dp_phy(void)
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 670e1cedf5..eac0e343bf 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -19,11 +19,11 @@
  * MA 02110-1301 USA
  */
 
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/pci_ids.h>
+#include <halt.h>
 #include <string.h>
 #include "me.h"
 #include "pch.h"
@@ -194,7 +194,7 @@ int intel_early_me_init_done(u8 status)
 	/* Perform the requested reset */
 	if (reset) {
 		outb(reset, 0xcf9);
-		hlt();
+		halt();
 	}
 	return -1;
 }
diff --git a/src/southbridge/intel/bd82x6x/early_me_native.c b/src/southbridge/intel/bd82x6x/early_me_native.c
index f327aec8c5..15e40871a9 100644
--- a/src/southbridge/intel/bd82x6x/early_me_native.c
+++ b/src/southbridge/intel/bd82x6x/early_me_native.c
@@ -19,11 +19,11 @@
  * MA 02110-1301 USA
  */
 
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/pci_ids.h>
+#include <halt.h>
 #include <string.h>
 #include "me.h"
 #include "pch.h"
@@ -184,7 +184,7 @@ int intel_early_me_init_done(u8 status)
 			pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
 			set_global_reset(0);
 			outb(0x6, 0xcf9);
-			hlt();
+			halt();
 		}
 
 		if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
@@ -266,7 +266,7 @@ int intel_early_me_init_done(u8 status)
 	/* Perform the requested reset */
 	if (reset) {
 		outb(reset, 0xcf9);
-		hlt();
+		halt();
 	}
 	return -1;
 }
diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c
index 5cd6315430..0863f3462c 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_native.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_native.c
@@ -19,7 +19,6 @@
 
 #include <console/console.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 44c72733dc..901e71dd5e 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -28,7 +28,6 @@
  */
 
 #include <arch/acpi.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
@@ -36,6 +35,7 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
+#include <halt.h>
 
 #ifdef __SMM__
 #include <arch/pci_mmio_cfg.h>
@@ -486,7 +486,7 @@ int mkhi_global_reset(void)
 	/* Send request and wait for response */
 	if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
 		/* No response means reset will happen shortly... */
-		hlt();
+		halt();
 	}
 
 	/* If the ME responded it rejected the reset request */
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 2dc83f708a..e25b3b8c4f 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -28,7 +28,6 @@
  */
 
 #include <arch/acpi.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
@@ -36,6 +35,7 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
+#include <halt.h>
 
 #ifdef __SMM__
 #include <arch/pci_mmio_cfg.h>
@@ -452,7 +452,7 @@ static int mkhi_global_reset(void)
 	printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__);
 	if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
 		/* No response means reset will happen shortly... */
-		hlt();
+		halt();
 	}
 
 	/* If the ME responded it rejected the reset request */
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index f886ad4432..1b8810f368 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -20,13 +20,13 @@
  */
 
 #include <types.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
 #include <cpu/x86/smm.h>
 #include <elog.h>
+#include <halt.h>
 #include <pc80/mc146818rtc.h>
 #include "pch.h"
 
@@ -474,7 +474,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 
 	/* In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake
diff --git a/src/southbridge/intel/fsp_bd82x6x/early_me.c b/src/southbridge/intel/fsp_bd82x6x/early_me.c
index 670e1cedf5..eac0e343bf 100644
--- a/src/southbridge/intel/fsp_bd82x6x/early_me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/early_me.c
@@ -19,11 +19,11 @@
  * MA 02110-1301 USA
  */
 
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/pci_ids.h>
+#include <halt.h>
 #include <string.h>
 #include "me.h"
 #include "pch.h"
@@ -194,7 +194,7 @@ int intel_early_me_init_done(u8 status)
 	/* Perform the requested reset */
 	if (reset) {
 		outb(reset, 0xcf9);
-		hlt();
+		halt();
 	}
 	return -1;
 }
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index 2282378997..5326eb5402 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -29,7 +29,6 @@
  */
 
 #include <arch/acpi.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
@@ -37,6 +36,7 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
+#include <halt.h>
 
 #ifndef __SMM__
 # include <device/device.h>
@@ -485,7 +485,7 @@ int mkhi_global_reset(void)
 	/* Send request and wait for response */
 	if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
 		/* No response means reset will happen shortly... */
-		hlt();
+		halt();
 	}
 
 	/* If the ME responded it rejected the reset request */
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index 1c2ab34ac5..d673ac783c 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -28,7 +28,6 @@
  */
 
 #include <arch/acpi.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
@@ -36,6 +35,7 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
+#include <halt.h>
 
 #ifndef __SMM__
 # include <device/device.h>
@@ -451,7 +451,7 @@ static int mkhi_global_reset(void)
 	printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__);
 	if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
 		/* No response means reset will happen shortly... */
-		hlt();
+		halt();
 	}
 
 	/* If the ME responded it rejected the reset request */
diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c
index fc09712e2b..b5e67d808a 100644
--- a/src/southbridge/intel/fsp_bd82x6x/reset.c
+++ b/src/southbridge/intel/fsp_bd82x6x/reset.c
@@ -20,7 +20,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <reset.h>
 
 void soft_reset(void)
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index b4fe557f54..493a98e146 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -20,13 +20,13 @@
  */
 
 #include <types.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
 #include <cpu/x86/smm.h>
 #include <elog.h>
+#include <halt.h>
 #include <pc80/mc146818rtc.h>
 #include "pch.h"
 
@@ -408,7 +408,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 
 	/* In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake
diff --git a/src/southbridge/intel/fsp_rangeley/reset.c b/src/southbridge/intel/fsp_rangeley/reset.c
index b6a0f3d9bf..3123514d92 100644
--- a/src/southbridge/intel/fsp_rangeley/reset.c
+++ b/src/southbridge/intel/fsp_rangeley/reset.c
@@ -20,7 +20,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <reset.h>
 
 void soft_reset(void)
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index cccfe150fb..4959c4dfd0 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -20,12 +20,12 @@
  */
 
 #include <types.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_def.h>
+#include <halt.h>
 #include <pc80/mc146818rtc.h>
 #include "i82801gx.h"
 
@@ -348,7 +348,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 	/* In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake
 	 * up again, we will continue to execute code in this function.
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 99920f55a2..f94b17fab9 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -28,7 +28,6 @@
  */
 
 #include <arch/acpi.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index bc4ca22c59..b6ca5235dd 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -20,13 +20,13 @@
  */
 
 #include <types.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
 #include <cpu/x86/smm.h>
 #include <elog.h>
+#include <halt.h>
 #include <pc80/mc146818rtc.h>
 #include "pch.h"
 
@@ -474,7 +474,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 
 	/* In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index c8ff913824..dfed6de774 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -28,7 +28,6 @@
  */
 
 #include <arch/acpi.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
@@ -38,6 +37,7 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
+#include <halt.h>
 
 #include "me.h"
 #include "pch.h"
@@ -563,7 +563,7 @@ static int mkhi_global_reset(void)
 	printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__);
 	if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) {
 		/* No response means reset will happen shortly... */
-		hlt();
+		halt();
 	}
 
 	/* If the ME responded it rejected the reset request */
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 00e4a839f4..627c64fc7b 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -22,13 +22,13 @@
 
 #include <delay.h>
 #include <types.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
 #include <cpu/x86/smm.h>
 #include <elog.h>
+#include <halt.h>
 #include <pc80/mc146818rtc.h>
 #include "pch.h"
 
@@ -199,7 +199,7 @@ static void southbridge_smi_sleep(void)
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 
 	/* In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake
-- 
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