From 5384da40b205b0088b1430bce3ab1cc014aeb286 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 23 Jul 2021 11:00:17 +0200 Subject: mb/siemens/mc_ehl1: Enable In Band ECC Enable IBECC for mc_ehl1 to provide a memory failure protection. Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564 Reviewed-by: Mario Scheithauer Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 34a4ce596b..1eece7aeed 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -20,6 +20,12 @@ chip soc/intel/elkhartlake register "SmbusEnable" = "1" register "Heci2Enable" = "1" + # Enable IBECC for the complete memory + register "ibecc" = "{ + .enable = 1, + .mode = IBECC_ALL + }" + # USB related UPDs register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1 register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2 -- cgit v1.2.3