From 53523dc2a4044d4e7a695524823290a98adbec43 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Wed, 22 May 2024 17:48:44 +0200
Subject: soc/amd/phoenix/chip_opensil.h: add missing include guards

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iba17d44772333ed59e3fdde1443a1862bae8e32f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82606
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
---
 src/soc/amd/phoenix/chip_opensil.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src')

diff --git a/src/soc/amd/phoenix/chip_opensil.h b/src/soc/amd/phoenix/chip_opensil.h
index da25a79a55..37170ad453 100644
--- a/src/soc/amd/phoenix/chip_opensil.h
+++ b/src/soc/amd/phoenix/chip_opensil.h
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#ifndef PHOENIX_CHIP_OPENSIL_H
+#define PHOENIX_CHIP_OPENSIL_H
+
 #include <types.h>
 
 #define DDI_DESCRIPTOR_COUNT	5
@@ -78,3 +81,5 @@ struct usb_phy_config {
 	uint8_t			PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
 	uint8_t			ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
 };
+
+#endif /* PHOENIX_CHIP_OPENSIL_H */
-- 
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