From 528ae9e811939c5e453c57aea79bc420a5f5fc43 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 28 Feb 2020 17:20:05 -0800 Subject: soc/tigerlake: Correct FSP log interface Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index d76961515f..f0f3b4cadd 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -61,7 +61,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* UART Debug Log */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : + DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; m_cfg->PcdIsaSerialUartBase = 0x0; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; -- cgit v1.2.3