From 50987a7b9e08139829da84958deea7f8bde3d376 Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Wed, 19 Jul 2017 16:19:46 +0530 Subject: vendercode/intel/fsp/skykabylake: Add new UPD SpiFlashCfgLockDown A new UPD named SpiFlashCfgLockDown is added in the FSP-S header file. This change is going to come in FSP in the next FSP release. This patch is pushed to urgently fix the SPI FPR locking issue. CQ-DEPEND=CL:*414049 BUG=b:63049493 BRANCH=none TEST=Built and boot poppy Change-Id: I4725506103781a358b18ee70f4fdd56bf4ab3d96 Signed-off-by: Barnali Sarkar Reviewed-on: https://review.coreboot.org/20644 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h index e91bc796bf..b3c7698857 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -165,9 +165,16 @@ typedef struct { **/ UINT8 ShowSpiController; -/** Offset 0x0036 +/** Offset 0x0036 - Flash Configuration Lock Down + Enable/disable flash lock down. If platform decides to skip this programming, it + must lock SPI flash register before end of post. + $EN_DIS +**/ + UINT8 SpiFlashCfgLockDown; + +/** Offset 0x0037 **/ - UINT8 UnusedUpdSpace0[2]; + UINT8 UnusedUpdSpace0; /** Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates -- cgit v1.2.3