From 4eed5e905760d6a029fe6d010143d24df055172b Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Wed, 15 Jul 2020 16:29:08 +0300 Subject: mb/ocp/tiogapass: Use macro to configure IIO Use macros to configure each of the IIO ports instead of an array of some unknown parameters. This will clean up the code and make it easier to read. Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical. Change-Id: I2911992435a6c93624525426d56212f821abb866 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502 Reviewed-by: Angel Pons Reviewed-by: Jonathan Zhang Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h | 79 +++++++++++----------- 1 file changed, 38 insertions(+), 41 deletions(-) (limited to 'src') diff --git a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h index 43b207e4d5..b66d7735d1 100644 --- a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h @@ -39,51 +39,48 @@ static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = { { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ }; +#define CFG_UPD_PORT(port, hide) \ + { \ + .PortIndex = port, \ + .HidePort = hide, \ + .DeEmphasis = 0x00, \ + .PortLinkSpeed = PcieAuto, \ + .MaxPayload = 0x00, \ + .DfxDnTxPreset = 0xFF, \ + .DfxRxPreset = 0xFF, \ + .DfxUpTxPreset = 0xFF, \ + .Sris = 0x00, \ + .PcieCommonClock = 0x00, \ + .NtbPpd = NTB_PORT_TRANSPARENT, \ + .NtbSplitBar = 0x00, \ + .NtbBarSizePBar23 = 0x16, \ + .NtbBarSizePBar4 = 0x16, \ + .NtbBarSizePBar5 = 0x16, \ + .NtbBarSizePBar45 = 0x16, \ + .NtbBarSizeSBar23 = 0x16, \ + .NtbBarSizeSBar4 = 0x16, \ + .NtbBarSizeSBar5 = 0x16, \ + .NtbBarSizeSBar45 = 0x16, \ + .NtbSBar01Prefetch = 0x00, \ + .NtbXlinkCtlOverride = 0x03, \ + } + /* * Standard Tioga Pass Iio PCIe Port Table */ static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { - // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | - // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | - // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | - // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | - // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride - { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, + CFG_UPD_PORT(PORT_1A, NOT_HIDE), + CFG_UPD_PORT(PORT_1B, HIDE), + CFG_UPD_PORT(PORT_1C, HIDE), + CFG_UPD_PORT(PORT_1D, HIDE), + CFG_UPD_PORT(PORT_2A, NOT_HIDE), + CFG_UPD_PORT(PORT_2B, HIDE), + CFG_UPD_PORT(PORT_2C, HIDE), + CFG_UPD_PORT(PORT_2D, HIDE), + CFG_UPD_PORT(PORT_3A, NOT_HIDE), + CFG_UPD_PORT(PORT_3B, HIDE), + CFG_UPD_PORT(PORT_3C, NOT_HIDE), + CFG_UPD_PORT(PORT_3D, HIDE), }; /* -- cgit v1.2.3