From 4e3d2a16ff532cbb8dfe4ea5eda56a7c23e65f67 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 22 Feb 2024 16:40:07 +0100
Subject: vc/amd/opensil/genoa_poc/mpio/chip: fix typo in pcie_aspm enum name
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60ac259d2aa0bd500063a5c841ba33e576e022f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80702
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'src')
diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h
index 2ef3e8b233..64a8b3e010 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h
+++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h
@@ -43,7 +43,7 @@ enum pcie_link_speed {
};
/* Sync with PCIE_ASPM_TYPE */
-enum pcie_asmp {
+enum pcie_aspm {
aspm_disabled,
L0s,
L1,
@@ -57,7 +57,7 @@ struct vendorcode_amd_opensil_genoa_poc_mpio_config {
uint8_t gpio_group;
enum mpio_hotplug hotplug;
enum pcie_link_speed speed;
- enum pcie_asmp aspm;
+ enum pcie_aspm aspm;
uint8_t aspm_l1_1 : 1;
uint8_t aspm_l1_2 : 1;
uint8_t clock_pm : 1;
--
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