From 4cdd0979ca6241bd664d3feb18ee96b0621f9978 Mon Sep 17 00:00:00 2001 From: Vinod Polimera Date: Tue, 3 Mar 2020 11:22:56 +0530 Subject: sc7180: Add display 10nm phy & pll programming support Adds basic headers as well as source required for display dsi 10nm phy & pll programming. Changes in V1: - add struct overlays to model hardware registers. - remove typedef structures. - remove dead code such as dual dsi,split config etc. Changes in V2: - remove panel related header files. - update the bitclock calculation using edid parameters. - add phy timing calculation function. - update copyright license. Changes in V3: - update the mdss clock structure. - remove dsi_phy_configinfo_type struct. - remove unused struct fields. Changes in V4: - update clock apis. - remove unused structures. Change-Id: I8ff400922ae594f558cf73a5aaa433a3a93347c2 Signed-off-by: Vinod Polimera Reviewed-on: https://review.coreboot.org/c/coreboot/+/39613 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/Makefile.inc | 2 + src/soc/qualcomm/sc7180/display/dsi_phy.c | 765 +++++++++++++++++++++ src/soc/qualcomm/sc7180/display/dsi_phy_pll.c | 148 ++++ .../sc7180/include/soc/display/display_resources.h | 36 + .../qualcomm/sc7180/include/soc/display/dsi_phy.h | 67 ++ .../sc7180/include/soc/display/dsi_phy_pll.h | 26 + .../qualcomm/sc7180/include/soc/display/mdssreg.h | 464 +++++++++++++ 7 files changed, 1508 insertions(+) create mode 100644 src/soc/qualcomm/sc7180/display/dsi_phy.c create mode 100644 src/soc/qualcomm/sc7180/display/dsi_phy_pll.c create mode 100644 src/soc/qualcomm/sc7180/include/soc/display/display_resources.h create mode 100644 src/soc/qualcomm/sc7180/include/soc/display/dsi_phy.h create mode 100644 src/soc/qualcomm/sc7180/include/soc/display/dsi_phy_pll.h create mode 100644 src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h (limited to 'src') diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 4f2a311d07..fc1e3f67e7 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -59,6 +59,8 @@ ramstage-y += usb.c ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy.c b/src/soc/qualcomm/sc7180/display/dsi_phy.c new file mode 100644 index 0000000000..050a5d88f1 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi_phy.c @@ -0,0 +1,765 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HAL_DSI_PHY_PLL_READY_TIMEOUT_MS 150 /* ~15 ms */ +#define HAL_DSI_PHY_REFGEN_TIMEOUT_MS 150 /* ~15 ms */ + +#define DSI_MAX_REFRESH_RATE 95 +#define DSI_MIN_REFRESH_RATE 15 + +#define HAL_DSI_PLL_VCO_MIN_MHZ_2_2_0 1000 + +#define S_DIV_ROUND_UP(n, d) \ + (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d))) + +#define mult_frac(x, numer, denom)( \ +{ \ + typeof(x) quot = (x) / (denom); \ + typeof(x) rem = (x) % (denom); \ + (quot * (numer)) + ((rem * (numer)) / (denom)); \ +} \ +) + +struct dsi_phy_divider_lut_entry_type { + uint16_t pll_post_div; + uint16_t phy_post_div; +}; + +/* PLL divider LUTs */ +static struct dsi_phy_divider_lut_entry_type pll_dividerlut_dphy[] = { +/* pll post div will always be power of 2 */ + { 2, 11 }, + { 4, 5 }, + { 2, 9 }, + { 8, 2 }, + { 1, 15 }, + { 2, 7 }, + { 1, 13 }, + { 4, 3 }, + { 1, 11 }, + { 2, 5 }, + { 1, 9 }, + { 8, 1 }, + { 1, 7 }, + { 2, 3 }, + { 1, 5 }, + { 4, 1 }, + { 1, 3 }, + { 2, 1 }, + { 1, 1 } +}; + +enum dsi_laneid_type { + DSI_LANEID_0 = 0, + DSI_LANEID_1, + DSI_LANEID_2, + DSI_LANEID_3, + DSI_LANEID_CLK, + DSI_LANEID_MAX, + DSI_LANEID_FORCE_32BIT = 0x7FFFFFFF +}; + +struct dsi_phy_configtype { + uint32_t desired_bitclk_freq; + uint32_t bits_per_pixel; + uint32_t num_data_lanes; + uint32_t pclk_divnumerator; + uint32_t pclk_divdenominator; + + /* pixel clk source select */ + uint32_t phy_post_div; + uint32_t pll_post_div; +}; + +static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent, + s32 min_result, bool even) +{ + s32 v; + + v = (tmax - tmin) * percent; + v = S_DIV_ROUND_UP(v, 100) + tmin; + if (even && (v & 0x1)) + return MAX(min_result, v - 1); + + return MAX(min_result, v); +} + +static void mdss_dsi_phy_reset(void) +{ + write32(&dsi0_phy->phy_cmn_ctrl1, 0x40); + udelay(100); + write32(&dsi0_phy->phy_cmn_ctrl1, 0x0); +} + +static void mdss_dsi_power_down(void) +{ + /* power up DIGTOP & PLL */ + write32(&dsi0_phy->phy_cmn_ctrl0, 0x60); + + /* Disable PLL */ + write32(&dsi0_phy->phy_cmn_pll_ctrl, 0x0); + + /* Resync re-time FIFO OFF*/ + write32(&dsi0_phy->phy_cmn_rbuf_ctrl, 0x0); +} + +static void mdss_dsi_phy_setup_lanephy(enum dsi_laneid_type lane) +{ + uint32_t reg_val = 0; + uint32_t lprx_ctrl = 0; + uint32_t hstx_strength = 0x88; + uint32_t data_strength_lp_n = 0x5; + uint32_t data_strength_lp_p = 0x5; + uint32_t pemph_bottom = 0; + uint32_t pemph_top = 0; + uint32_t strength_override = 0; + uint32_t clk_lane = 0; + + if (lane == DSI_LANEID_CLK) + clk_lane = 1; + else + clk_lane = 0; + + if (lane == DSI_LANEID_0) + lprx_ctrl = 3; + + /* + * DSIPHY_STR_LP_N + * DSIPHY_STR_LP_P + */ + reg_val = ((data_strength_lp_n << 0x4) & 0xf0) | + (data_strength_lp_p & 0x0f); + + write32(&dsi0_phy->phy_ln_regs[lane].dln0_lptx_str_ctrl, reg_val); + + /* + * DSIPHY_LPRX_EN + * DSIPHY_CDRX_EN + * Transition from 0 to 1 for DLN0-3 CLKLN stays 0 + */ + write32(&dsi0_phy->phy_ln_regs[lane].dln0_lprx_ctrl, 0x0); + write32(&dsi0_phy->phy_ln_regs[lane].dln0_lprx_ctrl, lprx_ctrl); + + /* Pin Swap */ + write32(&dsi0_phy->phy_ln_regs[lane].dln0_pin_swap, 0x0); + + /* + * DSIPHY_HSTX_STR_HSTOP + * DSIPHY_HSTX_STR_HSBOT + */ + write32(&dsi0_phy->phy_ln_regs[lane].dln0_hstx_str_ctrl, hstx_strength); + + /* PGM Delay */ + write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[0], 0x0); + + /* DLN0_CFG1 */ + reg_val = (strength_override << 0x5) & 0x20; + write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[1], reg_val); + + /* DLN0_CFG2 */ + reg_val = ((pemph_bottom << 0x04) & 0xf0) | + (pemph_top & 0x0f); + + write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[2], reg_val); + write32(&dsi0_phy->phy_ln_regs[lane].dln0_offset_top_ctrl, 0x0); + write32(&dsi0_phy->phy_ln_regs[lane].dln0_offset_bot_ctrl, 0x0); + + /* + * DSIPHY_LPRX_DLY + * IS_CKLANE + */ + reg_val = (clk_lane << 0x07) & 0x80; + write32(&dsi0_phy->phy_ln_regs[lane].dln0_cfg[3], reg_val); + + reg_val = 0; + if (lane == DSI_LANEID_CLK) + reg_val = 1; + + write32(&dsi0_phy->phy_ln_regs[lane].dln0_tx_dctrl, reg_val); +} + +static void mdss_dsi_calculate_phy_timings(struct msm_dsi_phy_ctrl *timing, + struct dsi_phy_configtype *phy_cfg) +{ + const unsigned long bit_rate = phy_cfg->desired_bitclk_freq; + s32 ui, ui_x8; + s32 tmax, tmin; + s32 pcnt0 = 50; + s32 pcnt1 = 50; + s32 pcnt2 = 10; + s32 pcnt3 = 30; + s32 pcnt4 = 10; + s32 pcnt5 = 2; + s32 coeff = 1000; /* Precision, should avoid overflow */ + s32 hb_en, hb_en_ckln; + s32 temp; + + if (!bit_rate) + return; + + hb_en = 0; + timing->half_byte_clk_en = 0; + hb_en_ckln = 0; + + ui = mult_frac(1000000, coeff, bit_rate / 1000); + ui_x8 = ui << 3; + + temp = S_DIV_ROUND_UP(38 * coeff, ui_x8); + tmin = MAX(temp, 0); + temp = (95 * coeff) / ui_x8; + tmax = MAX(temp, 0); + timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); + + temp = 300 * coeff - (timing->clk_prepare << 3) * ui; + tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; + tmax = (tmin > 255) ? 511 : 255; + timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); + + tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8); + temp = 105 * coeff + 12 * ui - 20 * coeff; + tmax = (temp + 3 * ui) / ui_x8; + timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); + + temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8); + tmin = MAX(temp, 0); + temp = (85 * coeff + 6 * ui) / ui_x8; + tmax = MAX(temp, 0); + timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); + + temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui; + tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; + tmax = 255; + timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); + + tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1; + temp = 105 * coeff + 12 * ui - 20 * coeff; + tmax = (temp / ui_x8) - 1; + timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); + + temp = 50 * coeff + ((hb_en << 2) - 8) * ui; + timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); + + tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; + tmax = 255; + timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); + + temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui; + timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); + + temp = 60 * coeff + 52 * ui - 43 * ui; + tmin = DIV_ROUND_UP(temp, ui_x8) - 1; + tmax = 63; + timing->clk_post = linear_inter(tmax, tmin, pcnt2, 0, false); + + temp = 8 * ui + (timing->clk_prepare << 3) * ui; + temp += (((timing->clk_zero + 3) << 3) + 11) * ui; + temp += hb_en_ckln ? (((timing->hs_rqst << 3) + 4) * ui) : + (((timing->hs_rqst << 3) + 8) * ui); + tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; + tmax = 63; + if (tmin > tmax) { + temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false); + timing->clk_pre = temp >> 1; + timing->clk_pre_inc_by_2 = 1; + } else { + timing->clk_pre = linear_inter(tmax, tmin, pcnt2, 0, false); + timing->clk_pre_inc_by_2 = 0; + } + + timing->ta_go = 3; + timing->ta_sure = 0; + timing->ta_get = 4; + + printk(BIOS_INFO, "PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", + timing->clk_pre, timing->clk_post, + timing->clk_pre_inc_by_2, timing->clk_zero, + timing->clk_trail, timing->clk_prepare, timing->hs_exit, + timing->hs_zero, timing->hs_prepare, timing->hs_trail, + timing->hs_rqst); +} + +static enum cb_err mdss_dsi_phy_timings(struct msm_dsi_phy_ctrl *phy_timings) +{ + uint32_t reg_val = 0; + + /* + * Step 4 Common block including GlobalTiming Parameters + * BYTECLK_SEL + */ + reg_val = (0x02 << 3) & 0x18; + write32(&dsi0_phy->phy_cmn_glbl_ctrl, reg_val); + + /* VREG_CTRL */ + write32(&dsi0_phy->phy_cmn_vreg_ctrl, 0x59); + + /*HALFBYTECLK_EN*/ + write32(&dsi0_phy->phy_cmn_timing_ctrl[0], phy_timings->half_byte_clk_en); + + /* T_CLK_ZERO */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[1], phy_timings->clk_zero); + + /* T_CLK_PREPARE */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[2], phy_timings->clk_prepare); + + /* T_CLK_TRAIL */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[3], phy_timings->clk_trail); + + /* T_HS_EXIT */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[4], phy_timings->hs_exit); + + /* T_HS_ZERO */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[5], phy_timings->hs_zero); + + /* T_HS_PREPARE */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[6], phy_timings->hs_prepare); + + /* T_HS_TRAIL */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[7], phy_timings->hs_trail); + + /* T_HS_RQST */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[8], phy_timings->hs_rqst); + + /* T_TA_GO & T_TA_SURE */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[9], + phy_timings->ta_sure << 3 | phy_timings->ta_go); + + /* T_TA_GET */ + write32(&dsi0_phy->phy_cmn_timing_ctrl[10], phy_timings->ta_get); + + /*DSIPHY_TRIG3_CMD*/ + write32(&dsi0_phy->phy_cmn_timing_ctrl[11], 0x0); + + /* DSI clock out timing ctrl T_CLK_PRE & T_CLK_POST*/ + reg_val = ((phy_timings->clk_post << 8) | phy_timings->clk_pre); + write32(&dsi0->clkout_timing_ctrl, reg_val); + + /* DCTRL */ + write32(&dsi0_phy->phy_cmn_ctrl2, 0x40); + + return CB_SUCCESS; +} + +static enum cb_err dsi_phy_waitforrefgen(void) +{ + uint32_t timeout = HAL_DSI_PHY_REFGEN_TIMEOUT_MS; + uint32_t refgen = 0; + enum cb_err ret = CB_SUCCESS; + + while (!refgen) { + refgen = (read32(&dsi0_phy->phy_cmn_phy_status) & 0x1); + if (!refgen) { + udelay(100); + timeout--; + if (!timeout) { + /* timeout while polling the lock status */ + ret = CB_ERR; + break; + } + } + } + + return ret; +} + +static enum cb_err mdss_dsi_phy_commit(void) +{ + enum cb_err ret = CB_SUCCESS; + + ret = dsi_phy_waitforrefgen(); + if (ret) { + printk(BIOS_ERR, "%s: waitforrefgen error\n", __func__); + return ret; + } + + mdss_dsi_power_down(); + + /* Remove PLL, DIG and all lanes from pwrdn */ + write32(&dsi0_phy->phy_cmn_ctrl0, 0x7F); + + /* Lane enable */ + write32(&dsi0_phy->phy_cmn_dsi_lane_ctrl0, 0x1F); + + mdss_dsi_phy_setup_lanephy(DSI_LANEID_0); + mdss_dsi_phy_setup_lanephy(DSI_LANEID_1); + mdss_dsi_phy_setup_lanephy(DSI_LANEID_2); + mdss_dsi_phy_setup_lanephy(DSI_LANEID_3); + mdss_dsi_phy_setup_lanephy(DSI_LANEID_CLK); + + return ret; +} + +static void mdss_dsi_phy_setup(void) +{ + /* First reset phy */ + mdss_dsi_phy_reset(); + + /* commit phy settings */ + mdss_dsi_phy_commit(); +} + +static void dsi_phy_resync_fifo(void) +{ + /* Resync FIFO*/ + write32(&dsi0_phy->phy_cmn_rbuf_ctrl, 0x1); +} + +static void dsi_phy_pll_global_clk_enable(bool enable) +{ + uint32_t clk_cfg = read32(&dsi0_phy->phy_cmn_clk_cfg1); + uint32_t clk_enable = 0; + + /* Set CLK_EN */ + if (enable) + clk_enable = 1; + + clk_cfg &= ~0x20; + clk_cfg |= ((clk_enable << 0x5) & 0x20); + + /* clk cfg1 */ + write32(&dsi0_phy->phy_cmn_clk_cfg1, clk_cfg); +} + +static enum cb_err dsi_phy_pll_lock_detect(void) +{ + enum cb_err ret = CB_SUCCESS; + + /* Enable PLL */ + write32(&dsi0_phy->phy_cmn_pll_ctrl, 0x1); + + /* Wait for Lock */ + if (!wait_us(15000, read32(&phy_pll_qlink->pll_common_status_one) & 0x1)) { + /* timeout while polling the lock status */ + ret = CB_ERR; + printk(BIOS_ERR, "dsi pll lock detect timedout, error.\n"); + } + + return ret; +} + +static void dsi_phy_toggle_dln3_tx_dctrl(void) +{ + uint32_t reg_val = 0; + + reg_val = read32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl); + + /* clear bit 0 and keep all other bits including bit 2 */ + reg_val &= ~0x01; + + /* toggle bit 0 */ + write32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl, (0x01 | reg_val)); + write32(&dsi0_phy->phy_ln_regs[DSI_LANEID_3].dln0_tx_dctrl, 0x4); +} + +static void dsi_phy_pll_set_source(void) +{ + uint32_t clk_cfg = read32(&dsi0_phy->phy_cmn_clk_cfg1); + uint32_t dsi_clksel = 1; + + clk_cfg &= ~0x03; + clk_cfg |= ((dsi_clksel) & 0x3); + + /* clk cfg1 */ + write32(&dsi0_phy->phy_cmn_clk_cfg1, clk_cfg); +} + +static void dsi_phy_pll_bias_enable(bool enable) +{ + uint32_t reg_val = 0; + + /* Set BIAS_EN_MUX, BIAS_EN */ + if (enable) + reg_val = (0x01 << 6) | (0x01 << 7); + + /* pll system muxes */ + write32(&phy_pll_qlink->pll_system_muxes, reg_val); + +} + +static void dsi_phy_mnd_divider(struct dsi_phy_configtype *phy_cfg) +{ + uint32_t m_val = 1; + uint32_t n_val = 1; + + if (phy_cfg->bits_per_pixel == 18) { + switch (phy_cfg->num_data_lanes) { + case 1: + case 2: + m_val = 2; + n_val = 3; + break; + case 4: + m_val = 4; + n_val = 9; + break; + default: + break; + } + } else if ((phy_cfg->bits_per_pixel == 16) && + (phy_cfg->num_data_lanes == 3)) { + m_val = 3; + n_val = 8; + } else if ((phy_cfg->bits_per_pixel == 30) && + (phy_cfg->num_data_lanes == 4)) { + m_val = 2; + n_val = 3; + } + + /*Save M/N info */ + phy_cfg->pclk_divnumerator = m_val; + phy_cfg->pclk_divdenominator = n_val; +} + +static uint32_t dsi_phy_dsiclk_divider(struct dsi_phy_configtype *phy_cfg) +{ + uint32_t m_val = phy_cfg->pclk_divnumerator; + uint32_t n_val = phy_cfg->pclk_divdenominator; + uint32_t div_ctrl = 0; + + div_ctrl = (m_val * phy_cfg->bits_per_pixel) / + (n_val * phy_cfg->num_data_lanes * 2); + + return div_ctrl; +} + + +static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg) +{ + bool div_found = false; + uint32_t m_val = 1; + uint32_t n_val = 1; + uint32_t div_ctrl = 0; + uint32_t reg_val = 0; + uint32_t pll_post_div = 0; + uint32_t phy_post_div = 0; + uint64_t vco_freq_hz = 0; + uint64_t fval = 0; + uint64_t pll_output_freq_hz; + uint64_t desired_bitclk_hz; + uint64_t min_vco_freq_hz = 0; + uint32_t lut_max; + int i; + struct dsi_phy_divider_lut_entry_type *lut; + + /* use 1000Mhz */ + min_vco_freq_hz = (HAL_DSI_PLL_VCO_MIN_MHZ_2_2_0 * 1000000); + + dsi_phy_mnd_divider(phy_cfg); + + m_val = phy_cfg->pclk_divnumerator; + n_val = phy_cfg->pclk_divdenominator; + + /* Desired clock in MHz */ + desired_bitclk_hz = (uint64_t)phy_cfg->desired_bitclk_freq; + + /* D Phy */ + lut = pll_dividerlut_dphy; + lut_max = sizeof(pll_dividerlut_dphy) / sizeof(*lut); + lut += (lut_max - 1); + + /* PLL Post Div - from LUT + * Check the LUT in reverse order + */ + for (i = lut_max - 1; i >= 0; i--, lut--) { + fval = (uint64_t)lut->phy_post_div * + (uint64_t)lut->pll_post_div; + if (fval) { + if ((desired_bitclk_hz * fval) > min_vco_freq_hz) { + /* Range found */ + pll_post_div = lut->pll_post_div; + phy_post_div = lut->phy_post_div; + div_found = true; + break; + } + } + } + + if (div_found) { + phy_cfg->pll_post_div = pll_post_div; + phy_cfg->phy_post_div = phy_post_div; + + /*div_ctrl_7_4 */ + div_ctrl = dsi_phy_dsiclk_divider(phy_cfg); + + /* DIV_CTRL_7_4 DIV_CTRL_3_0 + * (DIV_CTRL_3_0 = PHY post divider ratio) + */ + reg_val = (div_ctrl << 0x04) & 0xf0; + reg_val |= (phy_post_div & 0x0f); + write32(&dsi0_phy->phy_cmn_clk_cfg0, reg_val); + + /* PLL output frequency = desired_bitclk_hz * phy_post_div */ + pll_output_freq_hz = desired_bitclk_hz * phy_post_div; + + /* VCO output freq*/ + vco_freq_hz = pll_output_freq_hz * pll_post_div; + + } + + return (unsigned long)vco_freq_hz; +} + +static void dsi_phy_pll_outputdiv_rate(struct dsi_phy_configtype *pll_cfg) +{ + /* Output divider */ + uint32_t pll_post_div = 0; + uint32_t reg_val = 0; + + pll_post_div = log2(pll_cfg->pll_post_div); + reg_val = pll_post_div & 0x3; + write32(&phy_pll_qlink->pll_outdiv_rate, reg_val); +} + +static enum cb_err dsi_phy_pll_calcandcommit(struct dsi_phy_configtype *phy_cfg) +{ + unsigned long vco_freq_hz; + enum cb_err ret = CB_SUCCESS; + + /* validate input parameters */ + if (!phy_cfg) { + return CB_ERR; + } else if ((phy_cfg->bits_per_pixel != 16) && + (phy_cfg->bits_per_pixel != 18) && + (phy_cfg->bits_per_pixel != 24)) { + /* Unsupported pixel bit depth */ + return CB_ERR; + } else if ((phy_cfg->num_data_lanes == 0) || + (phy_cfg->num_data_lanes > 4)) { + /* Illegal number of DSI data lanes */ + return CB_ERR; + } + + vco_freq_hz = dsi_phy_calc_clk_divider(phy_cfg); + if (!vco_freq_hz) { + /* bitclock too low - unsupported */ + printk(BIOS_ERR, "vco_freq_hz is 0, unsupported\n"); + return CB_ERR; + } + + /* Enable PLL bias */ + dsi_phy_pll_bias_enable(true); + + /* Set byte clk source */ + dsi_phy_pll_set_source(); + + dsi_phy_pll_outputdiv_rate(phy_cfg); + dsi_phy_pll_vco_10nm_set_rate(vco_freq_hz); + dsi_phy_toggle_dln3_tx_dctrl(); + + /* Steps 6,7 Start PLL & Lock */ + if (ret == CB_SUCCESS) + ret = dsi_phy_pll_lock_detect(); + + /* Step 8 - Resync Data Paths */ + if (ret == CB_SUCCESS) { + /* Global clock enable */ + dsi_phy_pll_global_clk_enable(true); + + /* Resync FIFOs */ + dsi_phy_resync_fifo(); + } + + return ret; +} + +static uint32_t dsi_calc_desired_bitclk(struct edid *edid, uint32_t num_lines, uint32_t bpp) +{ + uint64_t desired_bclk = 0; + uint32_t pixel_clock_in_hz; + + pixel_clock_in_hz = edid->mode.pixel_clock * KHz; + if (num_lines) { + desired_bclk = pixel_clock_in_hz * (uint64_t)bpp; + desired_bclk = desired_bclk/(uint64_t)(num_lines); + } + + printk(BIOS_INFO, "Desired bitclock: %uHz\n", (uint32_t)desired_bclk); + return (uint32_t)desired_bclk; +} + +static enum cb_err mdss_dsi_phy_pll_setup(struct edid *edid, + uint32_t num_of_lanes, uint32_t bpp) +{ + struct dsi_phy_configtype phy_cfg; + struct msm_dsi_phy_ctrl phy_timings; + enum cb_err ret; + + /* Setup the PhyStructure */ + memset(&phy_cfg, 0, sizeof(struct dsi_phy_configtype)); + memset(&phy_timings, 0, sizeof(struct msm_dsi_phy_ctrl)); + + phy_cfg.bits_per_pixel = bpp; + phy_cfg.num_data_lanes = num_of_lanes; + + /* desired DSI PLL bit clk freq in Hz */ + phy_cfg.desired_bitclk_freq = dsi_calc_desired_bitclk(edid, num_of_lanes, bpp); + + ret = dsi_phy_pll_calcandcommit(&phy_cfg); + if (ret) + return ret; + mdss_dsi_calculate_phy_timings(&phy_timings, &phy_cfg); + ret = mdss_dsi_phy_timings(&phy_timings); + + return ret; +} + +static enum cb_err enable_dsi_clk(void) +{ + enum cb_err ret; + uint32_t i = 0; + struct mdp_external_clock_entry clks[] = { + {.clk_type = MDSS_CLK_ESC0, .clk_secondary_source = 1}, + {.clk_type = MDSS_CLK_PCLK0, .clk_source = 1}, + {.clk_type = MDSS_CLK_BYTE0, .clk_source = 1}, + {.clk_type = MDSS_CLK_BYTE0_INTF, .clk_source = 1, + .clk_div = 2, .source_div = 2}, + }; + + for (i = 0; i < ARRAY_SIZE(clks); i++) { + /* Set Ext Source */ + ret = mdss_clock_configure(clks[i].clk_type, + clks[i].clk_source, + clks[i].clk_div, + clks[i].clk_pll_m, + clks[i].clk_pll_n, + clks[i].clk_pll_2d); + if (ret) { + printk(BIOS_ERR, + "mdss_clock_configure failed for %u\n", + clks[i].clk_type); + return CB_ERR; + } + + ret = mdss_clock_enable(clks[i].clk_type); + if (ret) { + printk(BIOS_ERR, + "mdss_clock_enable failed for %u\n", + clks[i].clk_type); + return CB_ERR; + } + } + + return ret; +} + +enum cb_err mdss_dsi_phy_10nm_init(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp) +{ + enum cb_err ret; + + /* Phy set up */ + mdss_dsi_phy_setup(); + ret = mdss_dsi_phy_pll_setup(edid, num_of_lanes, bpp); + enable_dsi_clk(); + + return ret; +} diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c b/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c new file mode 100644 index 0000000000..b01fc2e436 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VCO_DELAY_USEC 1 + +/* Bit definition of SSC control registers */ +#define SSC_CENTER BIT(0) +#define SSC_EN BIT(1) + +struct dsi_pll_regs { + u32 pll_prop_gain_rate; + u32 decimal_div_start; + u32 frac_div_start_low; + u32 frac_div_start_mid; + u32 frac_div_start_high; + u32 pll_clock_inverters; +}; + +static void dsi_pll_init_val(void) +{ + write32(&phy_pll_qlink->pll_core_input_override, 0x10); + write32(&phy_pll_qlink->pll_int_loop_settings, 0x3f); + write32(&phy_pll_qlink->pll_int_loop_settings_two, 0x0); + write32(&phy_pll_qlink->pll_analog_ctrls_four, 0x0); + write32(&phy_pll_qlink->pll_int_loop_ctrls, 0x80); + write32(&phy_pll_qlink->pll_freq_update_ctrl_overrides, 0x0); + write32(&phy_pll_qlink->pll_band_sel_cal_timer_low, 0x0); + write32(&phy_pll_qlink->pll_band_sel_cal_timer_high, 0x02); + write32(&phy_pll_qlink->pll_band_sel_cal_settings, 0x82); + write32(&phy_pll_qlink->pll_band_sel_min, 0x00); + write32(&phy_pll_qlink->pll_band_sel_max, 0xff); + write32(&phy_pll_qlink->pll_band_sel_pfilt, 0x00); + write32(&phy_pll_qlink->pll_band_sel_ifilt, 0x00); + write32(&phy_pll_qlink->pll_band_sel_cal_settings_two, 0x25); + write32(&phy_pll_qlink->pll_band_sel_cal_settings_four, 0x4f); + write32(&phy_pll_qlink->pll_band_sel_icode_high, 0x0a); + write32(&phy_pll_qlink->pll_band_sel_icode_low, 0x0); + write32(&phy_pll_qlink->pll_pll_gain, 0x42); + write32(&phy_pll_qlink->pll_icode_low, 0x00); + write32(&phy_pll_qlink->pll_icode_high, 0x00); + write32(&phy_pll_qlink->pll_lockdet, 0x30); + write32(&phy_pll_qlink->pll_fastlock_ctrl, 0x04); + write32(&phy_pll_qlink->pll_pass_out_override_one, 0x00); + write32(&phy_pll_qlink->pll_pass_out_override_two, 0x00); + write32(&phy_pll_qlink->pll_rate_change, 0x01); + write32(&phy_pll_qlink->pll_digital_timers, 0x08); + write32(&phy_pll_qlink->pll_dec_frac_muxes, 0x00); + write32(&phy_pll_qlink->pll_mash_ctrl, 0x03); + write32(&phy_pll_qlink->pll_ssc_mux_ctrl, 0x0); + write32(&phy_pll_qlink->pll_ssc_ctrl, 0x0); + write32(&phy_pll_qlink->pll_pll_fastlock_en_band, 0x03); + write32(&phy_pll_qlink->pll_freq_tune_accum_init_mux, 0x0); + write32(&phy_pll_qlink->pll_lock_min_delay, 0x19); + write32(&phy_pll_qlink->pll_spare_and_jpc_overrides, 0x0); + write32(&phy_pll_qlink->pll_bias_ctrl_1, 0x40); + write32(&phy_pll_qlink->pll_bias_ctrl_2, 0x20); + write32(&phy_pll_qlink->pll_alog_obsv_bus_ctrl_1, 0x0); +} + +static void dsi_pll_calc_dec_frac(struct dsi_pll_regs *regs, + unsigned long rate) +{ + u32 frac_bits = 18; + u64 pll_freq; + u64 divider; + u64 dec, dec_multiple; + u32 frac; + u64 multiplier; + + pll_freq = rate; + divider = SRC_XO_HZ * 2; + + multiplier = 1 << frac_bits; + dec_multiple = (pll_freq * multiplier) / divider; + frac = dec_multiple % multiplier; + + dec = dec_multiple / multiplier; + if (pll_freq <= 1900UL * MHz) + regs->pll_prop_gain_rate = 8; + else if (pll_freq <= 3000UL * MHz) + regs->pll_prop_gain_rate = 10; + else + regs->pll_prop_gain_rate = 12; + + if (pll_freq < 1100UL * MHz) + regs->pll_clock_inverters = 8; + else + regs->pll_clock_inverters = 0; + + regs->decimal_div_start = dec; + regs->frac_div_start_low = (frac & 0xff); + regs->frac_div_start_mid = (frac & 0xff00) >> 8; + regs->frac_div_start_high = (frac & 0x30000) >> 16; +} + +static void dsi_pll_commit(struct dsi_pll_regs *reg) +{ + write32(&phy_pll_qlink->pll_core_input_override, 0x12); + write32(&phy_pll_qlink->pll_decimal_div_start_1, reg->decimal_div_start); + write32(&phy_pll_qlink->pll_frac_div_start_low1, reg->frac_div_start_low); + write32(&phy_pll_qlink->pll_frac_div_start_mid1, reg->frac_div_start_mid); + write32(&phy_pll_qlink->pll_frac_div_start_high1, reg->frac_div_start_high); + write32(&phy_pll_qlink->pll_lockdet_rate[0], 0x40); + write32(&phy_pll_qlink->pll_lock_delay, 0x06); + write32(&phy_pll_qlink->pll_cmode, 0x10); + write32(&phy_pll_qlink->pll_clock_inverters, reg->pll_clock_inverters); +} + +static void dsi_pll_config_hzindep_reg(struct dsi_pll_regs *reg) +{ + write32(&phy_pll_qlink->pll_analog_ctrls_one, 0x80); + write32(&phy_pll_qlink->pll_analog_ctrls_two, 0x03); + write32(&phy_pll_qlink->pll_analog_ctrls_three, 0x00); + write32(&phy_pll_qlink->pll_dsm_divider, 0x00); + write32(&phy_pll_qlink->pll_feedback_divider, 0x4e); + write32(&phy_pll_qlink->pll_cal_settings, 0x40); + write32(&phy_pll_qlink->pll_band_sel_cal_settings_three, 0xba); + write32(&phy_pll_qlink->pll_freq_detect_settings_one, 0x0c); + write32(&phy_pll_qlink->pll_outdiv, 0x00); + write32(&phy_pll_qlink->pll_core_override, 0x00); + write32(&phy_pll_qlink->pll_digital_timers_two, 0x08); + write32(&phy_pll_qlink->pll_prop_gain_rate[0], reg->pll_prop_gain_rate); + write32(&phy_pll_qlink->pll_band_set_rate[0], 0xc0); + write32(&phy_pll_qlink->pll_gain_ifilt_band[0], 0xfa); + write32(&phy_pll_qlink->pll_fl_int_gain_pfilt_band[0], 0x4c); + write32(&phy_pll_qlink->pll_lock_override, 0x80); + write32(&phy_pll_qlink->pll_pfilt, 0x29); + write32(&phy_pll_qlink->pll_ifilt, 0x3f); +} + +void dsi_phy_pll_vco_10nm_set_rate(unsigned long rate) +{ + struct dsi_pll_regs regs; + + dsi_pll_init_val(); + dsi_pll_calc_dec_frac(®s, rate); + dsi_pll_commit(®s); + dsi_pll_config_hzindep_reg(®s); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/display/display_resources.h b/src/soc/qualcomm/sc7180/include/soc/display/display_resources.h new file mode 100644 index 0000000000..a81c66cbfe --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/display_resources.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_RESOURCES_H_ +#define _SOC_DISPLAY_RESOURCES_H_ + +#include + +#define MDP_MAX_CLOCK_NAME 30 + +/* MDP External Clocks Entry */ +struct mdp_external_clock_entry { + enum mdss_clock clk_type; + + /* Primary Clock Source */ + uint32_t clk_source; + + /* Secondary Clock source */ + uint32_t clk_secondary_source; + + /* Clock pre-divider */ + uint32_t clk_div; + + /* Clock M value */ + uint32_t clk_pll_m; + + /* Clock N value */ + uint32_t clk_pll_n; + + /* Clock 2D value */ + uint32_t clk_pll_2d; + + /* Clock may need source divider */ + uint32_t source_div; +}; + +#endif diff --git a/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy.h b/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy.h new file mode 100644 index 0000000000..91d7adee64 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_DSI_PHY_H +#define _SOC_DISPLAY_DSI_PHY_H + +#include +#include + +#define MAX_REGULATOR_CONFIG 7 +#define MAX_BIST_CONFIG 6 +#define MAX_TIMING_CONFIG 40 +#define MAX_LANE_CONFIG 45 +#define MAX_STRENGTH_CONFIG 10 +#define MAX_CTRL_CONFIG 4 +#define DMA_TPG_FIFO_LEN 64 + +struct msm_panel_info; +struct mipi_dsi_phy_ctrl { + uint32_t regulator[5]; + uint32_t timing[12]; + uint32_t ctrl[4]; + uint32_t strength[4]; + uint32_t pll[21]; +}; + +enum dsi_reg_mode { + DSI_PHY_REGULATOR_DCDC_MODE, + DSI_PHY_REGULATOR_LDO_MODE, +}; + +enum { + DSI_PLL_TYPE_10NM, + DSI_PLL_TYPE_MAX, +}; + +struct msm_dsi_phy_ctrl { + uint32_t clk_pre; + uint32_t clk_post; + uint32_t clk_zero; + uint32_t clk_trail; + uint32_t clk_prepare; + uint32_t hs_exit; + uint32_t hs_zero; + uint32_t hs_prepare; + uint32_t hs_trail; + uint32_t hs_rqst; + uint32_t ta_go; + uint32_t ta_sure; + uint32_t ta_get; + uint32_t half_byte_clk_en; + bool clk_pre_inc_by_2; +}; + +struct mdss_dsi_phy_ctrl { + uint32_t regulator[MAX_REGULATOR_CONFIG]; + uint32_t timing[MAX_TIMING_CONFIG]; + uint32_t ctrl[MAX_CTRL_CONFIG]; + uint32_t strength[MAX_STRENGTH_CONFIG]; + char bistCtrl[MAX_BIST_CONFIG]; + char laneCfg[MAX_LANE_CONFIG]; + enum dsi_reg_mode regulator_mode; + int pll_type; +}; + +enum cb_err mdss_dsi_phy_10nm_init(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp); + +#endif diff --git a/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy_pll.h b/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy_pll.h new file mode 100644 index 0000000000..7dcca988b4 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/dsi_phy_pll.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_DSI_PHY_PLL_H +#define _SOC_DISPLAY_DSI_PHY_PLL_H + +#include + +enum { + MDSS_DSI_PLL_10NM, + MDSS_UNKNOWN_PLL, +}; + +struct mdss_pll_vco_calc { + s32 div_frac_start1; + s32 div_frac_start2; + s32 div_frac_start3; + s64 dec_start1; + s64 dec_start2; + s64 pll_plllock_cmp1; + s64 pll_plllock_cmp2; + s64 pll_plllock_cmp3; +}; + +void dsi_phy_pll_vco_10nm_set_rate(unsigned long rate); + +#endif diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h new file mode 100644 index 0000000000..57a30220bf --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h @@ -0,0 +1,464 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DISPLAY_MDSS_REG_H_ +#define _SOC_DISPLAY_MDSS_REG_H_ + +#include +#include + +struct dsi_regs { + uint32_t hw_version; + uint32_t ctrl; + uint32_t reserved0[2]; + uint32_t video_mode_ctrl; + uint32_t reserved1[4]; + uint32_t video_mode_active_h; + uint32_t video_mode_active_v; + uint32_t video_mode_active_total; + uint32_t video_mode_active_hsync; + uint32_t video_mode_active_vsync; + uint32_t video_mode_active_vsync_vpos; + uint32_t cmd_mode_dma_ctrl; + uint32_t cmd_mode_mdp_ctrl; + uint32_t cmd_mode_mdp_dcs_cmd_ctrl; + uint32_t dma_cmd_offset; + uint32_t dma_cmd_length; + uint32_t reserved2[2]; + uint32_t cmd_mode_mdp_stream0_ctrl; + uint32_t cmd_mode_mdp_stream0_total; + uint32_t cmd_mode_mdp_stream1_ctrl; + uint32_t cmd_mode_mdp_stream1_total; + uint32_t reserved4[7]; + uint32_t trig_ctrl; + uint32_t reserved5[2]; + uint32_t cmd_mode_dma_sw_trigger; + uint32_t reserved6[3]; + uint32_t misr_cmd_ctrl; + uint32_t misr_video_ctrl; + uint32_t lane_status; + uint32_t lane_ctrl; + uint32_t reserved7[3]; + uint32_t hs_timer_ctrl; + uint32_t timeout_status; + uint32_t clkout_timing_ctrl; + uint32_t eot_packet; + uint32_t eot_packet_ctrl; + uint32_t reserved8[15]; + uint32_t err_int_mask0; + uint32_t int_ctrl; + uint32_t iobist_ctrl; + uint32_t soft_reset; + uint32_t clk_ctrl; + uint32_t reserved9[15]; + uint32_t test_pattern_gen_ctrl; + uint32_t reserved10[7]; + uint32_t test_pattern_gen_cmd_dma_init_val; + uint32_t reserved11[14]; + uint32_t cmd_mode_mdp_ctrl2; + uint32_t reserved12[12]; + uint32_t tpg_dma_fifo_reset; + uint32_t reserved13[44]; + uint32_t video_compression_mode_ctrl; + uint32_t video_compression_mode_ctrl2; + uint32_t cmd_compression_mode_ctrl; + uint32_t cmd_compression_mode_ctrl2; + uint32_t cmd_compression_mode_ctrl3; +}; + +check_member(dsi_regs, video_mode_active_h, 0x24); +check_member(dsi_regs, cmd_mode_mdp_stream0_ctrl, 0x58); +check_member(dsi_regs, trig_ctrl, 0x84); +check_member(dsi_regs, cmd_mode_dma_sw_trigger, 0x90); +check_member(dsi_regs, misr_cmd_ctrl, 0xA0); +check_member(dsi_regs, hs_timer_ctrl, 0xBC); +check_member(dsi_regs, err_int_mask0, 0x10C); +check_member(dsi_regs, test_pattern_gen_ctrl, 0x15c); +check_member(dsi_regs, test_pattern_gen_cmd_dma_init_val, 0x17c); +check_member(dsi_regs, cmd_mode_mdp_ctrl2, 0x1B8); +check_member(dsi_regs, tpg_dma_fifo_reset, 0x1EC); +check_member(dsi_regs, video_compression_mode_ctrl, 0x2A0); + +struct dsi_phy_regs { + uint32_t phy_cmn_revision_id0; + uint32_t reserved0[3]; + uint32_t phy_cmn_clk_cfg0; + uint32_t phy_cmn_clk_cfg1; + uint32_t phy_cmn_glbl_ctrl; + uint32_t phy_cmn_rbuf_ctrl; + uint32_t phy_cmn_vreg_ctrl; + uint32_t phy_cmn_ctrl0; + uint32_t phy_cmn_ctrl1; + uint32_t phy_cmn_ctrl2; + uint32_t phy_cmn_lane_cfg0; + uint32_t phy_cmn_lane_cfg1; + uint32_t phy_cmn_pll_ctrl; + uint32_t reserved1[23]; + uint32_t phy_cmn_dsi_lane_ctrl0; + uint32_t reserved2[4]; + uint32_t phy_cmn_timing_ctrl[12]; + uint32_t reserved3[4]; + uint32_t phy_cmn_phy_status; + uint32_t reserved4[68]; + struct { + uint32_t dln0_cfg[4]; + uint32_t dln0_test_datapath; + uint32_t dln0_pin_swap; + uint32_t dln0_hstx_str_ctrl; + uint32_t dln0_offset_top_ctrl; + uint32_t dln0_offset_bot_ctrl; + uint32_t dln0_lptx_str_ctrl; + uint32_t dln0_lprx_ctrl; + uint32_t dln0_tx_dctrl; + uint32_t reserved5[20]; + } phy_ln_regs[5]; +}; + +check_member(dsi_phy_regs, phy_cmn_clk_cfg0, 0x10); +check_member(dsi_phy_regs, phy_cmn_dsi_lane_ctrl0, 0x98); +check_member(dsi_phy_regs, phy_cmn_timing_ctrl[0], 0xAC); +check_member(dsi_phy_regs, phy_cmn_phy_status, 0xEC); +check_member(dsi_phy_regs, phy_ln_regs[0], 0x200); +check_member(dsi_phy_regs, phy_ln_regs[1], 0x280); +check_member(dsi_phy_regs, phy_ln_regs[2], 0x300); +check_member(dsi_phy_regs, phy_ln_regs[3], 0x380); +check_member(dsi_phy_regs, phy_ln_regs[4], 0x400); + +struct dsi_phy_pll_qlink_regs { + uint32_t pll_analog_ctrls_one; + uint32_t pll_analog_ctrls_two; + uint32_t pll_int_loop_settings; + uint32_t pll_int_loop_settings_two; + uint32_t pll_analog_ctrls_three; + uint32_t pll_analog_ctrls_four; + uint32_t pll_int_loop_ctrls; + uint32_t pll_dsm_divider; + uint32_t pll_feedback_divider; + uint32_t pll_system_muxes; + uint32_t pll_freq_update_ctrl_overrides; + uint32_t pll_cmode; + uint32_t pll_cal_settings; + uint32_t pll_band_sel_cal_timer_low; + uint32_t pll_band_sel_cal_timer_high; + uint32_t pll_band_sel_cal_settings; + uint32_t pll_band_sel_min; + uint32_t pll_band_sel_max; + uint32_t pll_band_sel_pfilt; + uint32_t pll_band_sel_ifilt; + uint32_t pll_band_sel_cal_settings_two; + uint32_t pll_band_sel_cal_settings_three; + uint32_t pll_band_sel_cal_settings_four; + uint32_t pll_band_sel_icode_high; + uint32_t pll_band_sel_icode_low; + uint32_t pll_freq_detect_settings_one; + uint32_t pll_freq_detect_thresh; + uint32_t pll_freq_det_refclk_high; + uint32_t pll_freq_det_refclk_low; + uint32_t pll_freq_det_pllclk_high; + uint32_t pll_freq_det_pllclk_low; + uint32_t pll_pfilt; + uint32_t pll_ifilt; + uint32_t pll_pll_gain; + uint32_t pll_icode_low; + uint32_t pll_icode_high; + uint32_t pll_lockdet; + uint32_t pll_outdiv; + uint32_t pll_fastlock_ctrl; + uint32_t pll_pass_out_override_one; + uint32_t pll_pass_out_override_two; + uint32_t pll_core_override; + uint32_t pll_core_input_override; + uint32_t pll_rate_change; + uint32_t pll_digital_timers; + uint32_t pll_digital_timers_two; + uint32_t pll_decimal_div_start; + uint32_t pll_frac_div_start_low; + uint32_t pll_frac_div_start_mid; + uint32_t pll_frac_div_start_high; + uint32_t pll_dec_frac_muxes; + uint32_t pll_decimal_div_start_1; + uint32_t pll_frac_div_start_low1; + uint32_t pll_frac_div_start_mid1; + uint32_t pll_frac_div_start_high1; + uint32_t reserve0[4]; + uint32_t pll_mash_ctrl; + uint32_t reserved1[6]; + uint32_t pll_ssc_mux_ctrl; + uint32_t pll_ssc_stepsize_low1; + uint32_t pll_ssc_stepsize_high1; + uint32_t pll_ssc_div_per_low_1; + uint32_t pll_ssc_div_per_high_1; + uint32_t pll_ssc_adjper_low_1; + uint32_t pll_ssc_adjper_high_1; + uint32_t reserved2[6]; + uint32_t pll_ssc_ctrl; + uint32_t pll_outdiv_rate; + uint32_t pll_lockdet_rate[2]; + uint32_t pll_prop_gain_rate[2]; + uint32_t pll_band_set_rate[2]; + uint32_t pll_gain_ifilt_band[2]; + uint32_t pll_fl_int_gain_pfilt_band[2]; + uint32_t pll_pll_fastlock_en_band; + uint32_t reserved9[3]; + uint32_t pll_freq_tune_accum_init_mux; + uint32_t pll_lock_override; + uint32_t pll_lock_delay; + uint32_t pll_lock_min_delay; + uint32_t pll_clock_inverters; + uint32_t pll_spare_and_jpc_overrides; + uint32_t pll_bias_ctrl_1; + uint32_t pll_bias_ctrl_2; + uint32_t pll_alog_obsv_bus_ctrl_1; + uint32_t pll_common_status_one; +}; + +check_member(dsi_phy_pll_qlink_regs, pll_mash_ctrl, 0xEC); +check_member(dsi_phy_pll_qlink_regs, pll_ssc_mux_ctrl, 0x108); +check_member(dsi_phy_pll_qlink_regs, pll_ssc_ctrl, 0x13C); +check_member(dsi_phy_pll_qlink_regs, pll_freq_tune_accum_init_mux, 0x17C); + +struct mdp_intf_regs { + uint32_t timing_eng_enable; + uint32_t intf_config; + uint32_t intf_hsync_ctl; + uint32_t intf_vysnc_period_f0; + uint32_t intf_vysnc_period_f1; + uint32_t intf_vysnc_pulse_width_f0; + uint32_t intf_vysnc_pulse_width_f1; + uint32_t intf_disp_v_start_f0; + uint32_t intf_disp_v_start_f1; + uint32_t intf_disp_v_end_f0; + uint32_t intf_disp_v_end_f1; + uint32_t intf_active_v_start_f0; + uint32_t intf_active_v_start_f1; + uint32_t intf_active_v_end_f0; + uint32_t intf_active_v_end_f1; + uint32_t intf_disp_hctl; + uint32_t intf_active_hctl; + uint32_t intf_border_color; + uint32_t intf_underflow_color; + uint32_t reserved0[17]; + uint32_t intf_panel_format; + uint32_t reserved1[55]; + uint32_t intf_prof_fetch_start; + uint32_t reserved2[58]; + uint32_t intf_mux; +}; + +check_member(mdp_intf_regs, intf_panel_format, 0x90); +check_member(mdp_intf_regs, intf_prof_fetch_start, 0x170); +check_member(mdp_intf_regs, intf_mux, 0x25C); + +struct mdp_ctl_regs { + uint32_t ctl_layer0; + uint32_t ctl_layer1; + uint32_t reserved0[3]; + uint32_t ctl_top; + uint32_t ctl_flush; + uint32_t ctl_start; + uint32_t reserved1[53]; + uint32_t ctl_intf_active; + uint32_t reserved2[6]; + uint32_t ctl_intf_flush; +}; + +check_member(mdp_ctl_regs, ctl_top, 0x14); +check_member(mdp_ctl_regs, ctl_intf_active, 0xF4); +check_member(mdp_ctl_regs, ctl_intf_flush, 0x110); + +struct mdp_layer_mixer_regs { + uint32_t layer_op_mode; + uint32_t layer_out_size; + uint32_t layer_border_color_0; + uint32_t layer_border_color_1; + uint32_t reserved0[4]; + struct { + uint32_t layer_blend_op; + uint32_t layer_blend_const_alpha; + uint32_t layer_blend_fg_color_fill_color0; + uint32_t layer_blend_fg_color_fill_color1; + uint32_t layer_blend_fg_fill_size; + uint32_t layer_blend_fg_fill_xy; + } layer_blend[6]; +}; + +struct mdp_sspp_regs { + uint32_t sspp_src_size; + uint32_t sspp_src_img_size; + uint32_t sspp_src_xy; + uint32_t sspp_out_size; + uint32_t sspp_out_xy; + uint32_t sspp_src0; + uint32_t sspp_src1; + uint32_t sspp_src2; + uint32_t sspp_src3; + uint32_t sspp_src_ystride0; + uint32_t sspp_src_ystride1; + uint32_t sspp_tile_frame_size; + uint32_t sspp_src_format; + uint32_t sspp_src_unpack_pattern; + uint32_t sspp_src_op_mode; + uint32_t reserved0[51]; + uint32_t sspp_sw_pic_ext_c0_req_pixels; + uint32_t reserved1[3]; + uint32_t sspp_sw_pic_ext_c1c2_req_pixels; + uint32_t reserved2[3]; + uint32_t sspp_sw_pic_ext_c3_req_pixels; +}; + +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c0_req_pixels, 0x108); +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c1c2_req_pixels, 0x118); +check_member(mdp_sspp_regs, sspp_sw_pic_ext_c3_req_pixels, 0x128); + +struct vbif_rt_regs { + uint32_t reserved0[88]; + uint32_t vbif_out_axi_amemtype_conf0; + uint32_t vbif_out_axi_amemtype_conf1; + uint32_t reserved1[250]; + struct { + uint32_t vbif_xinl_qos_rp_remap; + uint32_t vbif_xinh_qos_rp_remap; + } qos_rp_remap[8]; + struct { + uint32_t vbif_xinl_qos_lvl_remap; + uint32_t vbif_xinh_qos_lvl_remap; + } qos_lvl_remap[8]; +}; + +check_member(vbif_rt_regs, vbif_out_axi_amemtype_conf0, 0x160); +check_member(vbif_rt_regs, qos_rp_remap[0], 0x550); + +enum { + MDSS_BASE = 0xAE00000, +}; + +enum { + MDP_0_CTL_BASE = MDSS_BASE + 0x2000, + MDP_VP_0_SSPP_BASE = MDSS_BASE + 0x5000, + MDP_VP_0_LAYER_MIXER_BASE = MDSS_BASE + 0x45000, + MDP_1_INTF_BASE = MDSS_BASE + 0x6b800, + MDP_VBIF_RT_BASE = MDSS_BASE + 0xB0000, + DSI0_CTL_BASE = MDSS_BASE + 0x94000, + DSI0_PHY_BASE = MDSS_BASE + 0x94400, + DSI0_PHY_DLN0_BASE = MDSS_BASE + 0x94600, + DSI0_PHY_DLN1_BASE = MDSS_BASE + 0x94680, + DSI0_PHY_DLN2_BASE = MDSS_BASE + 0x94700, + DSI0_PHY_DLN3_BASE = MDSS_BASE + 0x94780, + DSI0_PHY_CLKLN_BASE = MDSS_BASE + 0x94800, + DSI0_PHY_PLL_QLINK_COM = MDSS_BASE + 0x94a00, +}; + +/* DSI_0_CLK_CTRL */ +enum { + INTF = BIT(31), + PERIPH = BIT(30), + CWB = BIT(28), + ROT = BIT(27), + CDM_0 = BIT(26), + DMA_3 = BIT(25), + DMA_2 = BIT(24), + MERGE_3D = BIT(23), + DSC = BIT(22), + DSPP_3 = BIT(21), + LAYER_MIXER_5 = BIT(20), + DSPP_PA_LUTV_3 = BIT(19), + VIG_3 = BIT(18), + CTL = BIT(17), + WB = BIT(16), + DSPP_2 = BIT(15), + DSPP_1 = BIT(14), + DSPP_0 = BIT(13), + DMA_1 = BIT(12), + DMA_0 = BIT(11), + LAYER_MIXER_4 = BIT(10), + LAYER_MIXER_3 = BIT(9), + LAYER_MIXER_2 = BIT(8), + LAYER_MIXER_1 = BIT(7), + LAYER_MIXER_0 = BIT(6), + DSPP_PA_LUTV_2 = BIT(5), + DSPP_PA_LUTV_1 = BIT(4), + DSPP_PA_LUTV_0 = BIT(3), + VIG_2 = BIT(2), + VIG_1 = BIT(1), + VIG_0 = BIT(0), +}; + +enum { + DSI_AHBS_HCLK_ON = BIT(0), + DSI_AHBM_SCLK_ON = BIT(1), + DSI_PCLK_ON = BIT(2), + DSI_DSICLK_ON = BIT(3), + DSI_BYTECLK_ON = BIT(4), + DSI_ESCCLK_ON = BIT(5), + DSI_FORCE_ON_DYN_AHBS_HCLK = BIT(8), + DSI_FORCE_ON_DYN_AHBM_HCLK = BIT(9), + DSI_FORCE_ON_DYN_DSICLK = BIT(10), + DSI_FORCE_ON_DYN_BYTECLK = BIT(11), + DSI_AHBS_HCLK_HYSTERISIS1_CTRL = (3 << 11), + DSI_AHBM_HCLK_HYSTERISIS1_CTRL = (3 << 13), + DSI_DSICLK_HYSTERISIS1_CTRL = (3 << 15), + DSI_FORCE_ON_DYN_PCLK = BIT(20), + DSI_FORCE_ON_LANE_LAYER_TG_BYTECLK = BIT(21), + DSI_DMA_CLK_STOP = BIT(22), +}; + +/* DSI_0_INT_CTRL */ +enum { + DSI_CMD_MODE_DMA_DONE_AK = BIT(0), + DSI_CMD_MODE_DMA_DONE_STAT = BIT(0), + DSI_CMD_MODE_DMA_DONE_MASK = BIT(1), + DSI_CMD_MODE_MDP_DONE_AK = BIT(8), + DSI_CMD_MODE_MDP_DONE_STAT = BIT(8), + DSI_CMD_MODE_MDP_DONE_MASK = BIT(9), + DSI_CMD_MDP_STREAM0_DONE_AK = BIT(10), + DSI_CMD_MDP_STREAM0_DONE_STAT = BIT(10), + DSI_CMD_MDP_STREAM0_DONE_MASK = BIT(11), + DSI_VIDEO_MODE_DONE_AK = BIT(16), + DSI_VIDEO_MODE_DONE_STAT = BIT(16), + DSI_VIDEO_MODE_DONE_MASK = BIT(17), + DSI_BTA_DONE_AK = BIT(20), + DSI_BTA_DONE_STAT = BIT(20), + DSI_BTA_DONE_MASK = BIT(21), + DSI_ERROR_AK = BIT(24), + DSI_ERROR_STAT = BIT(24), + DSI_ERROR_MASK = BIT(25), + DSI_DYNAMIC_BLANKING_DMA_DONE_AK = BIT(26), + DSI_DYNAMIC_BLANKING_DMA_DONE_STAT = BIT(26), + DSI_DYNAMIC_BLANKING_DMA_DONE_MASK = BIT(27), + DSI_DYNAMIC_REFRESH_DONE_AK = BIT(28), + DSI_DYNAMIC_REFRESH_DONE_STAT = BIT(28), + DSI_DYNAMIC_REFRESH_DONE_MASK = BIT(29), + DSI_DESKEW_DONE_AK = BIT(30), + DSI_DESKEW_DONE_STAT = BIT(30), + DSI_DESKEW_DONE_MASK = BIT(31), +}; + +/* DSI_0_COMMAND_MODE_MDP_DCS_CMD_CTRL */ +enum { + WR_MEM_START = 255, + WR_MEM_CONTINUE = 255 << 8, + INSERT_DCS_COMMAND = BIT(16), +}; + +/* DSI_0_COMMAND_MODE_DMA_CTRL */ +enum { + PACKET_TYPE = BIT(24), + POWER_MODE = BIT(26), + EMBEDDED_MODE = BIT(28), + WC_SEL = BIT(29), + BROADCAST_MASTER = BIT(30), + BROADCAST_EN = BIT(31), +}; + +static struct dsi_regs *const dsi0 = (void *)DSI0_CTL_BASE; +static struct dsi_phy_regs *const dsi0_phy = (void *)DSI0_PHY_BASE; +static struct dsi_phy_pll_qlink_regs *const phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM; +static struct mdp_intf_regs *const mdp_intf = (void *)MDP_1_INTF_BASE; +static struct mdp_ctl_regs *const mdp_ctl = (void *)MDP_0_CTL_BASE; +static struct mdp_layer_mixer_regs *const mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE; +static struct mdp_sspp_regs *const mdp_sspp = (void *)MDP_VP_0_SSPP_BASE; +static struct vbif_rt_regs *const vbif_rt = (void *)MDP_VBIF_RT_BASE; + +void mdp_dsi_video_config(struct edid *edid); +void mdp_dsi_video_on(void); + +#endif -- cgit v1.2.3