From 4b75b44bd8c315a81793651152aa71d7451dbcd0 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Wed, 15 Dec 2021 10:25:32 -0700 Subject: mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGE Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3. BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3 Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/guybrush/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 7d9cd3d0a0..ded66ab0a6 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -39,6 +39,7 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select PSP_DISABLE_POSTCODES + select PSP_S0I3_RESUME_VERSTAGE if VBOOT_STARTS_BEFORE_BOOTBLOCK select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select SOC_AMD_COMMON_BLOCK_USE_ESPI -- cgit v1.2.3