From 4b10dec1a66122b515b2191f823d7fd379ec655f Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Sat, 14 Feb 2015 02:00:32 -0600 Subject: cpu/allwinner/a10/Kconfig: Link ramstage at base of SDRAM The default linking behavior of ramstage was changed in commit * 8f99378 ARMv7/Exynos: Fix memory location assumptions However, that commit failed to address the issue of maintaining linking behavior on non-Exynos chips. As a result we ended up linking ramstage at address 0, which is outside of SDRAM. Explicitly link ramstage at SDRAM base for A10. This patch does not address the issue on other chips that were broken by commit 8f99378. Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083 Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/8443 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/allwinner/a10/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 27049052d3..e38227b755 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -36,6 +36,11 @@ config CBFS_HEADER_ROM_OFFSET config CBFS_ROM_OFFSET default 0x5fc0 +# Arbitrarily chosen to be at the base of SDRAM +config RAMSTAGE_BASE + hex + default SYS_SDRAM_BASE + # 16 MiB above ramstage, so there is no overlap config ROMSTAGE_BASE hex -- cgit v1.2.3