From 49c44cdccb936bf1179402b5927a1f477ad4e752 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 May 2020 08:52:07 +0300 Subject: arch/x86: Remove XIP_ROM_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When adding XIP stages on x86, the -P parameter was used to pass a page size that covers the entire file to add. The same can now be achieved with --pow2page and we no longer need to define a static Konfig for the purpose. TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and inspect the generated make.log files. The effective pagesize is reduced from 64kB to 16kB for asus/p2b giving more freedom for the stage placement inside CBFS. Pagesize remained at 64kB for lenovo/x60. Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820 Tested-by: build bot (Jenkins) Reviewed-by: Keith Hui Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- src/cpu/x86/Kconfig | 5 ----- src/include/cpu/x86/mtrr.h | 4 ---- 2 files changed, 9 deletions(-) (limited to 'src') diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 4260278e02..07dfe45e64 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -70,11 +70,6 @@ config NO_FIXED_XIP_ROM_SIZE to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened. -config XIP_ROM_SIZE - hex - depends on !NO_FIXED_XIP_ROM_SIZE - default 0x10000 - config SETUP_XIP_CACHE bool depends on !NO_XIP_EARLY_STAGES diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 412330449f..9227710596 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -190,10 +190,6 @@ static inline unsigned int fls(unsigned int x) */ #define CACHE_TMP_RAMTOP (16<<20) -#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) -# error "CONFIG_XIP_ROM_SIZE is not a power of 2" -#endif - /* For ROM caching, generally, try to use the next power of 2. */ #define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) #define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE) -- cgit v1.2.3