From 46cef44dad8f796b9c5ac0ed3a684266b88cec62 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 23 Jan 2020 00:12:46 -0800 Subject: mb/intel/tglrvp: Enable DP ports for TGLRVP TGLRVP uses DdiPort1Hpd and DdiPort1Ddc. So only enable them. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim Change-Id: Ief6376ba59c77340e272923958b6b5f0a1456d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38529 Reviewed-by: Furquan Shaikh Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e7bfe337f9..d4b5a39bfd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -49,6 +49,12 @@ chip soc/intel/tigerlake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + # enabling EDP in PortA + register "DdiPortAConfig" = "1" + + register "DdiPort1Hpd" = "1" + register "DdiPort1Ddc" = "1" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, -- cgit v1.2.3