From 4493f66904b1cb4fb33a7d9d08f6f137ebb3c780 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Mon, 9 Sep 2024 12:36:58 +0100
Subject: mb/starlabs/starbook/cml: Alphabetize and group FSP UPDs

Change-Id: I063062d875be61875da136228db06a39bc434833
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/mainboard/starlabs/starbook/variants/cml/devicetree.cb | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index df8bd990ec..0070f22374 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -1,7 +1,8 @@
 chip soc/intel/cannonlake
-	# CPU
-	# Enable Enhanced Intel SpeedStep
+	# FSP UPDs
 	register "eist_enable"			= "true"
+	register "enable_c6dram"		= "1"
+	register "SaGv"				= "SaGv_Enabled"
 
 	# Graphics
 	# IGD Displays
@@ -14,11 +15,6 @@ chip soc/intel/cannonlake
 		.backlight_pwm_hz		=  200,				// PWM
 	}"
 
-	# FSP Memory
-	register "enable_c6dram"		= "1"
-	register "SaGv"				= "SaGv_Enabled"
-
-	# FSP Silicon
 	# Serial I/O
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
-- 
cgit v1.2.3