From 44526cd1fc06f1a037fc74053db6ab6c7866d20e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 3 May 2017 18:49:28 +0200 Subject: nb/intel/sandybridge/early_init: Use register name Use names instead of magic values. No functional change. Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/19547 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Reviewed-by: Sumeet R Pawnikar --- src/northbridge/intel/sandybridge/early_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 16ea29da67..efe27b1b29 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -30,10 +30,10 @@ static void sandybridge_setup_bars(void) { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ printk(BIOS_DEBUG, " done.\n"); -- cgit v1.2.3