From 43825e89607db06ac96926ab9872887980fb2ad3 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 13 Dec 2018 09:26:39 -0800 Subject: mb/google/sarien: Enable DMI/SATA power Optimize Turn on power optimizer of PCH side DMI and SATA controller. BUG=N/A TEST=Build and boot up into sarien platoform, able to finish 100 cycles of s0ix. Signed-off-by: Lijian Zhao Change-Id: I41da2b4106d683945cdc296e2a77311176144f43 Reviewed-on: https://review.coreboot.org/c/30212 Tested-by: build bot (Jenkins) Reviewed-by: Roy Mingi Park Reviewed-by: Duncan Laurie --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 ++ src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 ++ 2 files changed, 4 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index acdb623319..a8bb34233a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,6 +27,8 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 2800ff588c..c24cd028e1 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -31,6 +31,8 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port -- cgit v1.2.3