From 42fcb2a8f4f9b395ceb84f7d644864c596b0a9a2 Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Wed, 10 Nov 2021 05:22:47 +0530 Subject: libpayload: Parse DDR Information using coreboot tables BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193 Reviewed-by: Shelley Chen Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- .../bsd/include/commonlib/bsd/mem_chip_info.h | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h (limited to 'src') diff --git a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h new file mode 100644 index 0000000000..7194f70174 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _COMMONLIB_BSD_MEM_CHIP_INFO_H_ +#define _COMMONLIB_BSD_MEM_CHIP_INFO_H_ + +enum mem_chip_type { + MEM_CHIP_DDR3 = 0x30, + MEM_CHIP_LPDDR3 = 0x38, + MEM_CHIP_DDR4 = 0x40, + MEM_CHIP_LPDDR4 = 0x48, + MEM_CHIP_LPDDR4X = 0x49, +}; + +struct mem_chip_info { + uint8_t type; /* enum mem_chip_type */ + uint8_t num_channels; + uint8_t reserved[6]; + struct { + uint64_t density; + uint8_t io_width; + uint8_t manufacturer_id; + uint8_t revision_id[2]; + uint8_t reserved[4]; + uint8_t serial_id[8]; /* LPDDR5 only */ + } channel[0]; +}; + +#endif /* _COMMONLIB_BSD_MEM_CHIP_INFO_H_ */ -- cgit v1.2.3