From 426e07aaf20ae917dd65997bf46667d56881444a Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Tue, 8 Sep 2020 11:30:46 +0530 Subject: mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20W Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W. BRANCH=None BUG=b:166656373 TEST=Built and tested on drawlat system Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162 Reviewed-by: Paul Menzel Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 395dee3f69..fa10152a4e 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -59,7 +59,7 @@ chip soc/intel/jasperlake register "power_limits_config" = "{ .tdp_pl1_override = 6, - .tdp_pl2_override = 15, + .tdp_pl2_override = 20, }" register "tcc_offset" = "20" # TCC of 85C @@ -93,7 +93,7 @@ chip soc/intel/jasperlake .granularity = 200,}" register "controls.power_limits.pl2" = "{ .min_power = 6000, - .max_power = 15000, + .max_power = 20000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, .granularity = 1000,}" -- cgit v1.2.3