From 40f0dafd141d7f97c7295c892f10a10967c775aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 20 Dec 2022 00:24:46 +0200 Subject: google/zork: Convert baseboard directory layout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are two baseboards within the set of mainboards built here, with baseboard name appended in the filenames. Take the style and variable BASEBOARD_DIR from google/brya, then move and rename the supporting files under separate directories. Change-Id: I2046b6f82519540b8596ce925203bd60d1870c1c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74471 Reviewed-by: Felix Held Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/Kconfig | 8 +- src/mainboard/google/zork/Makefile.inc | 3 + .../google/zork/variants/baseboard/Makefile.inc | 44 +-- .../zork/variants/baseboard/dalboz/Makefile.inc | 19 + .../zork/variants/baseboard/dalboz/devicetree.cb | 391 ++++++++++++++++++ .../google/zork/variants/baseboard/dalboz/fsps.c | 73 ++++ .../google/zork/variants/baseboard/dalboz/gpio.c | 368 +++++++++++++++++ .../zork/variants/baseboard/devicetree_dalboz.cb | 391 ------------------ .../zork/variants/baseboard/devicetree_trembyle.cb | 439 --------------------- .../variants/baseboard/fsps_baseboard_dalboz.c | 73 ---- .../variants/baseboard/fsps_baseboard_trembyle.c | 184 --------- .../variants/baseboard/gpio_baseboard_dalboz.c | 368 ----------------- .../variants/baseboard/gpio_baseboard_trembyle.c | 417 ------------------- .../zork/variants/baseboard/trembyle/Makefile.inc | 20 + .../zork/variants/baseboard/trembyle/devicetree.cb | 439 +++++++++++++++++++++ .../google/zork/variants/baseboard/trembyle/fsps.c | 184 +++++++++ .../google/zork/variants/baseboard/trembyle/gpio.c | 417 +++++++++++++++++++ 17 files changed, 1921 insertions(+), 1917 deletions(-) create mode 100644 src/mainboard/google/zork/variants/baseboard/dalboz/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb create mode 100644 src/mainboard/google/zork/variants/baseboard/dalboz/fsps.c create mode 100644 src/mainboard/google/zork/variants/baseboard/dalboz/gpio.c delete mode 100644 src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb delete mode 100644 src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb delete mode 100644 src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c delete mode 100644 src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c delete mode 100644 src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c delete mode 100644 src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c create mode 100644 src/mainboard/google/zork/variants/baseboard/trembyle/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb create mode 100644 src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c create mode 100644 src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c (limited to 'src') diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 68c5ba1a60..3481810d68 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -88,9 +88,13 @@ config MAINBOARD_PART_NUMBER default "Shuboz" if BOARD_GOOGLE_SHUBOZ default "Gumboz" if BOARD_GOOGLE_GUMBOZ +config BASEBOARD_DIR + string + default "trembyle" if BOARD_GOOGLE_BASEBOARD_TREMBYLE + default "dalboz" if BOARD_GOOGLE_BASEBOARD_DALBOZ + config DEVICETREE - default "variants/baseboard/devicetree_trembyle.cb" if BOARD_GOOGLE_BASEBOARD_TREMBYLE - default "variants/baseboard/devicetree_dalboz.cb" if BOARD_GOOGLE_BASEBOARD_DALBOZ + default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb" config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index a260b0fd21..df809cb488 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -13,6 +13,9 @@ ramstage-y += sku_id.c verstage-y += chromeos.c verstage-y += verstage.c +BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR)) + +subdirs-y += variants/baseboard/$(BASEBOARD_DIR) subdirs-y += variants/baseboard subdirs-y += variants/$(VARIANT_DIR)/spd subdirs-y += spd diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index 437ba0b52c..2a35748b03 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -1,57 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += helpers.c -bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c -bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c +all-y += helpers.c -verstage-y += helpers.c -verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c -verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c verstage-y += tpm_tis.c - -romstage-y += helpers.c -romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c -romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c romstage-y += tpm_tis.c - -ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c -ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += fsps_baseboard_trembyle.c -ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c -ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += fsps_baseboard_dalboz.c -ramstage-y += helpers.c ramstage-y += tpm_tis.c ramstage-y += ramstage_common.c -smm-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c -smm-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c - # Add OEM ID table ifeq ($(CONFIG_USE_OEM_BIN),y) cbfs-files-y += oem.bin oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) oem.bin-type := raw endif #($(CONFIG_USE_OEM_BIN),y) - -# APCB Board ID GPIO configuration. -# These GPIOs determine which memory SPD will be used during boot. -# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL -# GPIO_NUMBER: FCH GPIO number -# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO -# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO -# APCB_POPULATE_2ND_CHANNEL: Populates 2nd memory channel in APCB when true. -# Trembyle based boards select 1 or 2 channels based on AGPIO84 -# Dalboz based boards only support 1 channel -ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y) -APCB_BOARD_ID_GPIO0 = 121 1 0 -APCB_BOARD_ID_GPIO1 = 120 1 0 -APCB_BOARD_ID_GPIO2 = 131 3 0 -APCB_BOARD_ID_GPIO3 = 116 1 0 -APCB_POPULATE_2ND_CHANNEL = true -else ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ),y) -APCB_BOARD_ID_GPIO0 = 132 1 0 -APCB_BOARD_ID_GPIO1 = 90 1 0 -APCB_BOARD_ID_GPIO2 = 86 3 0 -APCB_BOARD_ID_GPIO3 = 69 1 0 -else -$(error Undefined APCB selection GPIOS for Zork baseboard) -endif #($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y) diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/dalboz/Makefile.inc new file mode 100644 index 0000000000..66dc17512b --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/dalboz/Makefile.inc @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +all-y += gpio.c +smm-y += gpio.c +ramstage-y += fsps.c + +# APCB Board ID GPIO configuration. +# These GPIOs determine which memory SPD will be used during boot. +# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL +# GPIO_NUMBER: FCH GPIO number +# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO +# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO +# APCB_POPULATE_2ND_CHANNEL: Populates 2nd memory channel in APCB when true. +# Trembyle based boards select 1 or 2 channels based on AGPIO84 +# Dalboz based boards only support 1 channel +APCB_BOARD_ID_GPIO0 = 132 1 0 +APCB_BOARD_ID_GPIO1 = 90 1 0 +APCB_BOARD_ID_GPIO2 = 86 3 0 +APCB_BOARD_ID_GPIO3 = 69 1 0 diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb new file mode 100644 index 0000000000..68eb6ea588 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb @@ -0,0 +1,391 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +fw_config + field TOUCHPAD 26 + option REGULAR_TOUCHPAD 1 + option NUMPAD_TOUCHPAD 0 + end +end + +chip soc/amd/picasso + + # Set FADT Configuration + register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + # See table 5-34 ACPI 6.3 spec + register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" + + # ACP Configuration + register "common_config.acp_config" = "{ + .acp_pin_cfg = I2S_PINS_I2S_TDM, + .acp_i2s_wake_enable = 0, + .acp_pme_enable = 0, + }" + + # Start : OPN Performance Configuration + # (Configuration that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time_ms" = "20" + + # Lower die temperature limit + register "thermctl_limit_degreeC" = "100" + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin_mV" = "0" + register "vddcr_vdd_voltage_margin_mV" = "0" + + # VRM Limits + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + /* + * The reference design was missing a pull-up on the CMD line. + * This means we can't run at the full 400 kHz. By setting this + * to 1 we run at the slowest frequency possible by the + * controller (~97 kHz). + * + * Boards that have the pull-up should correctly set this. + */ + .init_khz_preset = 1, + }" + + register "has_usb2_phy_tune_params" = "1" + + # Controller0 Port0 Default + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port1 Default + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port2 Default + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port3 Default + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port0 Default + register "usb_2_port_tune_params[4]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port1 Default + register "usb_2_port_tune_params[5]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Start RV2 USB3 PHY Parameters + register "usb3_phy_override" = "0" + + # USB3 Port0 Default + register "usb3_phy_tune_params[0]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port1 Default + register "usb3_phy_tune_params[1]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port2 Default + register "usb3_phy_tune_params[2]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port3 Default + register "usb3_phy_tune_params[3]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # SUP_DIG_LVL_OVRD_IN Default + register "usb3_rx_vref_ctrl" = "0x10" + register "usb3_rx_vref_ctrl_en" = "0x00" + register "usb_3_tx_vboost_lvl" = "0x07" + register "usb_3_tx_vboost_lvl_en" = "0x00" + + # SUPX_DIG_LVL_OVRD_IN Default + register "usb_3_rx_vref_ctrl_x" = "0x10" + register "usb_3_rx_vref_ctrl_en_x" = "0x00" + register "usb_3_tx_vboost_lvl_x" = "0x07" + register "usb_3_tx_vboost_lvl_en_x" = "0x00" + + # End RV2 USB3 phy setting + + # USB OC pin mapping + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB A1 + register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera + register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + + register "pspp_policy" = "DXIO_PSPP_BALANCED" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device ref iommu on end + device ref gpp_bridge_1 on # Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end + device ref gpp_bridge_2 on end # SD + device ref internal_bridge_a on + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)" + device usb 2.5 alias xhci0_bt on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.3 on end + end + end + end + end + device ref acp on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5682"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 0.0 alias acp_machine on end + end + end # Audio + device ref hda off end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device + end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a alias audio_rt5682 on end + end + end + end + chip ec/google/chromeec/audio_codec + register "uid" = "1" + device generic 0 on end + end + end + end + end + end # domain + + device ref i2c_3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + + device ref uart_0 on end # console + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/fsps.c b/src/mainboard/google/zork/variants/baseboard/dalboz/fsps.c new file mode 100644 index 0000000000..992d89661f --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/dalboz/fsps.c @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); +} + +static const fsp_dxio_descriptor dxio_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + } +}; + +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) +{ + *num = ARRAY_SIZE(dxio_descriptors); + return dxio_descriptors; +} + +const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +{ + /* Different configurations of dalboz have different ddi configurations. + * Therefore, don't provide any baseboard defaults. */ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/gpio.c b/src/mainboard/google/zork/variants/baseboard/dalboz/gpio.c new file mode 100644 index 0000000000..5c5933920b --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/dalboz/gpio.c @@ -0,0 +1,368 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* PEN_DETECT_ODL */ + PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), + /* PEN_POWER_EN - Enabled*/ + PAD_GPO(GPIO_5, HIGH), + /* EN_PWR_TOUCHPAD */ + PAD_GPO(GPIO_6, HIGH), + /* I2S_SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S_LRCLK - Bit banged in depthcharge */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* TOUCHPAD_INT_ODL */ + PAD_SCI(GPIO_9, PULL_NONE, LEVEL_LOW), + /* S0iX SLP - goes to EC */ + PAD_GPO(GPIO_10, HIGH), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_11, PULL_NONE), + /* USI_INT_ODL */ + PAD_GPI(GPIO_12, PULL_NONE), + /* GPIO_13 - GPIO_15: Not available */ + /* USB_OC0_L - USB C0/A0 */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* USB_OC1_L - USB C1 */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), + /* WIFI_DISABLE */ + PAD_GPO(GPIO_18, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EMMC_CMD */ + PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), + /* EC_FCH_SCI_ODL */ + PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* GPIO_27: Configured in bootblock. */ + /* GPIO_28: Not available */ + /* GPIO_29: Handled in bootblock for wifi power/reset control. */ + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* EC_AP_INT_ODL (Sensor Framesync) */ + PAD_GPI(GPIO_31, PULL_NONE), + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_32, HIGH), + /* GPIO_33 - GPIO_39: Not available */ + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* GPIO_41: Not available */ + /* GPIO_42: Handled in bootblock for wifi power/reset control. */ + /* GPIO_43 - GPIO_66: Not available */ + /* DMIC_SEL */ + /* + * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash + * access will be very slow. + */ + PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic + /* EMMC_RESET_L */ + PAD_GPO(GPIO_68, HIGH), + /* RAM ID 3 */ + PAD_GPI(GPIO_69, PULL_NONE), + /* EMMC_CLK */ + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ + /* EMMC_DATA4 */ + PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), + /* EMMC_DATA6 */ + PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, HIGH), + /* GPIO_77 - GPIO_83: Not available */ + /* HP_INT_ODL */ + PAD_GPI(GPIO_84, PULL_NONE), + /* APU_EDP_BL_DISABLE */ + PAD_GPO(GPIO_85, LOW), + /* RAM ID 2 - Keep High */ + PAD_GPO(GPIO_86, HIGH), + /* EMMC_DATA7 */ + PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), + /* EMMC_DATA5 */ + PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), + /* GPIO_89 - unused */ + PAD_NC(GPIO_89), + /* RAM ID 1 */ + PAD_GPI(GPIO_90, PULL_NONE), + /* EN_SPKR */ + PAD_GPO(GPIO_91, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ + /* EMMC_DATA0 */ + PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), + /* EMMC_DATA1 */ + PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), + /* EMMC_DATA2 */ + PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), + /* EMMC_DATA3 */ + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* EMMC_DS */ + PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* GPIO_110 - GPIO112: Not available */ + /* I2C2_SCL - USI/Touchpad */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA - USI/Touchpad */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L - NVMe */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* GPIO_117 - GPIO_128: Not available */ + /* KBRST_L */ + PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* GPIO_130 - GPIO_131: Not available */ + /* RAM ID 0 */ + PAD_GPI(GPIO_132, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ + /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ + PAD_GPI(GPIO_135, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* DEV_BEEP_BCLK */ + PAD_GPI(GPIO_139, PULL_NONE), + /* TOUCHSCREEN_RESET_L */ + PAD_GPO(GPIO_140, HIGH), + /* USB_HUB_RST_L */ + PAD_GPO(GPIO_141, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), + /* BT_DISABLE */ + PAD_GPO(GPIO_143, LOW), + /* USI_REPORT_EN */ + PAD_GPO(GPIO_144, LOW), +}; + +const struct soc_amd_gpio *baseboard_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + +static void wifi_power_reset_configure_active_low_power(void) +{ + /* + * Configure WiFi GPIOs such that: + * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device. + * - Enable power to WiFi using EN_PWR_WIFI_L. + * - Wait for 50ms after power to WiFi is enabled. + * - Deassert WIFI_AUX_RESET. + */ + static const struct soc_amd_gpio v3_wifi_table[] = { + /* WIFI_AUX_RESET */ + PAD_GPO(GPIO_29, HIGH), + /* EN_PWR_WIFI_L */ + PAD_GPO(GPIO_42, LOW), + }; + gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); + + mdelay(50); + gpio_set(GPIO_29, 0); +} + +static void wifi_power_reset_configure_active_high_power(void) +{ + /* + * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET + * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be + * set low before driving it high to trigger a WiFi power cycle to meet PCIe + * requirements. Thus, configure GPIOs such that: + * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device + * - Disable power to WiFi. + * - Wait 10ms for WiFi power to go low. + * - Enable power to WiFi using EN_PWR_WIFI. + * - Deassert WIFI_AUX_RESET. + */ + static const struct soc_amd_gpio v3_wifi_table[] = { + /* WIFI_AUX_RESET */ + PAD_GPO(GPIO_29, HIGH), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_42, LOW), + }; + gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); + + mdelay(10); + gpio_set(GPIO_42, 1); + mdelay(50); + gpio_set(GPIO_29, 0); +} + +static void wifi_power_reset_configure_v3(void) +{ + if (variant_has_active_low_wifi_power()) + wifi_power_reset_configure_active_low_power(); + else + wifi_power_reset_configure_active_high_power(); +} + +static void wifi_power_reset_configure_pre_v3(void) +{ + /* + * Configure WiFi GPIOs such that: + * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. + * - Disable power to WiFi since GPIO_29 goes high on PWRGOOD but has a glitch on RESET# + * deassertion causing WiFi to enter a bad state. + * - Wait 10ms for WiFi power to go low. + * - Enable power to WiFi using EN_PWR_WIFI. + * - Wait for 50ms after power to WiFi is enabled. + * - Deassert WIFI_AUX_RESET_L. + */ + static const struct soc_amd_gpio pre_v3_wifi_table[] = { + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_42, LOW), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, LOW), + }; + gpio_configure_pads(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table)); + + mdelay(10); + gpio_set(GPIO_29, 1); + mdelay(50); + gpio_set(GPIO_42, 1); +} + +void baseboard_pcie_gpio_configure(void) +{ + static const struct soc_amd_gpio pcie_gpio_table[] = { + /* PCIE_RST1_L - Variable timings (May remove) */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L - NVMe */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), + }; + + gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); + + /* Deassert PCIE_RST1_L */ + gpio_set(GPIO_27, 1); + + if (variant_uses_v3_schematics()) + wifi_power_reset_configure_v3(); + else + wifi_power_reset_configure_pre_v3(); +} + +__weak void finalize_gpios(int slp_typ) +{ +} + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + *size = 0; + return NULL; +} + +static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), + /* PCIE_RST1_L */ + PAD_GPO(GPIO_27, LOW), + /* + * On pre-v3 schematics, GPIO_29 is EN_PWR_WIFI. So, setting to high should be no-op. + * On v3+ schematics, GPIO_29 is WIFI_AUX_RESET. Setting to high ensures that PERST# is + * asserted to WiFi device until coreboot reconfigures GPIO_29 on resume path. + */ + PAD_GPO(GPIO_29, HIGH), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), +}; + +const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) +{ + *size = ARRAY_SIZE(gpio_sleep_table); + return gpio_sleep_table; +} + +static const struct soc_amd_gpio espi_gpio_table[] = { + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_11, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + +static const struct soc_amd_gpio early_gpio_table[] = { + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct soc_amd_gpio romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_32, HIGH), + /* TOUCHSCREEN_RESET_L */ + PAD_GPO(GPIO_140, LOW), +}; + +const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb deleted file mode 100644 index 68eb6ea588..0000000000 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ /dev/null @@ -1,391 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -fw_config - field TOUCHPAD 26 - option REGULAR_TOUCHPAD 1 - option NUMPAD_TOUCHPAD 0 - end -end - -chip soc/amd/picasso - - # Set FADT Configuration - register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - # See table 5-34 ACPI 6.3 spec - register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" - - # ACP Configuration - register "common_config.acp_config" = "{ - .acp_pin_cfg = I2S_PINS_I2S_TDM, - .acp_i2s_wake_enable = 0, - .acp_pme_enable = 0, - }" - - # Start : OPN Performance Configuration - # (Configuration that is common for all variants) - # For the below fields, 0 indicates use SOC default - - # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time_ms" = "20" - - # Lower die temperature limit - register "thermctl_limit_degreeC" = "100" - - # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit_mA" = "18000" - register "psi0_soc_current_limit_mA" = "12000" - register "vddcr_soc_voltage_margin_mV" = "0" - register "vddcr_vdd_voltage_margin_mV" = "0" - - # VRM Limits - register "vrm_maximum_current_limit_mA" = "0" - register "vrm_soc_maximum_current_limit_mA" = "0" - register "vrm_current_limit_mA" = "0" - register "vrm_soc_current_limit_mA" = "0" - - # Misc SMU settings - register "sb_tsi_alert_comparator_mode_en" = "0" - register "core_dldo_bypass" = "1" - register "min_soc_vid_offset" = "0" - register "aclk_dpm0_freq_400MHz" = "0" - - # End : OPN Performance Configuration - - register "emmc_config" = "{ - .timing = SD_EMMC_EMMC_HS400, - .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, - /* - * The reference design was missing a pull-up on the CMD line. - * This means we can't run at the full 400 kHz. By setting this - * to 1 we run at the slowest frequency possible by the - * controller (~97 kHz). - * - * Boards that have the pull-up should correctly set this. - */ - .init_khz_preset = 1, - }" - - register "has_usb2_phy_tune_params" = "1" - - # Controller0 Port0 Default - register "usb_2_port_tune_params[0]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x03, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x6, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller0 Port1 Default - register "usb_2_port_tune_params[1]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x03, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x6, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller0 Port2 Default - register "usb_2_port_tune_params[2]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x03, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x6, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller0 Port3 Default - register "usb_2_port_tune_params[3]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x03, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x6, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller1 Port0 Default - register "usb_2_port_tune_params[4]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x02, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x5, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller1 Port1 Default - register "usb_2_port_tune_params[5]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x02, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x5, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Start RV2 USB3 PHY Parameters - register "usb3_phy_override" = "0" - - # USB3 Port0 Default - register "usb3_phy_tune_params[0]" = "{ - .rx_eq_delta_iq_ovrd_val = 0x0, - .rx_eq_delta_iq_ovrd_en = 0x0, - }" - - # USB3 Port1 Default - register "usb3_phy_tune_params[1]" = "{ - .rx_eq_delta_iq_ovrd_val = 0x0, - .rx_eq_delta_iq_ovrd_en = 0x0, - }" - - # USB3 Port2 Default - register "usb3_phy_tune_params[2]" = "{ - .rx_eq_delta_iq_ovrd_val = 0x0, - .rx_eq_delta_iq_ovrd_en = 0x0, - }" - - # USB3 Port3 Default - register "usb3_phy_tune_params[3]" = "{ - .rx_eq_delta_iq_ovrd_val = 0x0, - .rx_eq_delta_iq_ovrd_en = 0x0, - }" - - # SUP_DIG_LVL_OVRD_IN Default - register "usb3_rx_vref_ctrl" = "0x10" - register "usb3_rx_vref_ctrl_en" = "0x00" - register "usb_3_tx_vboost_lvl" = "0x07" - register "usb_3_tx_vboost_lvl_en" = "0x00" - - # SUPX_DIG_LVL_OVRD_IN Default - register "usb_3_rx_vref_ctrl_x" = "0x10" - register "usb_3_rx_vref_ctrl_en_x" = "0x00" - register "usb_3_tx_vboost_lvl_x" = "0x07" - register "usb_3_tx_vboost_lvl_en_x" = "0x00" - - # End RV2 USB3 phy setting - - # USB OC pin mapping - register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 - register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1" # USB C1 - register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" # USB A0 - register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB A1 - register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera - register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth - - # eSPI Configuration - register "common_config.espi_config" = "{ - .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, - .generic_io_range[0] = { - .base = 0x62, - /* - * Only 0x62 and 0x66 are required. But, this is not supported by - * standard IO decodes and there are only 4 generic I/O windows - * available. Hence, open a window from 0x62-0x67. - */ - .size = 5, - }, - .generic_io_range[1] = { - .base = 0x800, /* EC_HOST_CMD_REGION0 */ - .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ - }, - .generic_io_range[2] = { - .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ - .size = 255, /* EC_MEMMAP_SIZE */ - }, - .generic_io_range[3] = { - .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ - .size = 8, /* 0x200 - 0x207 */ - }, - - .io_mode = ESPI_IO_MODE_QUAD, - .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, - .crc_check_enable = 1, - .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, - .periph_ch_en = 1, - .vw_ch_en = 1, - .oob_ch_en = 0, - .flash_ch_en = 0, - - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), - }" - - register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - - # general purpose PCIe clock output configuration - register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN - register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader - register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD - register "gpp_clk_config[3]" = "GPP_CLK_OFF" - register "gpp_clk_config[4]" = "GPP_CLK_OFF" - register "gpp_clk_config[5]" = "GPP_CLK_OFF" - register "gpp_clk_config[6]" = "GPP_CLK_OFF" - - register "pspp_policy" = "DXIO_PSPP_BALANCED" - - # See AMD 55570-B1 Table 13: PCI Device ID Assignments. - device domain 0 on - subsystemid 0x1022 0x1510 inherit - device ref iommu on end - device ref gpp_bridge_1 on # Wifi - chip drivers/wifi/generic - register "wake" = "GEVENT_8" - device pci 00.0 on end - end - end - device ref gpp_bridge_2 on end # SD - device ref internal_bridge_a on - device ref gfx on end # Internal GPU - device ref gfx_hda on end # Display HDA - device ref crypto on end # Crypto Coprocessor - device ref xhci_0 on # USB 3.1 - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""User-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)" - device usb 2.5 alias xhci0_bt on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.3 on end - end - end - end - end - device ref acp on - chip drivers/amd/i2s_machine_dev - register "hid" = ""AMDI5682"" - # DMIC select GPIO for ACP machine device - # This GPIO is used to select DMIC0 or DMIC1 by the - # kernel driver. It does not really have a polarity - # since low and high control the selection of DMIC and - # hence does not have an active polarity. - # Kernel driver does not use the polarity field and - # instead treats the GPIO selection as follows: - # Set low (0) = Select DMIC0 - # Set high (1) = Select DMIC1 - register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" - device generic 0.0 alias acp_machine on end - end - end # Audio - device ref hda off end # HDA - device ref mp2 on end # non-Sensor Fusion Hub device - end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 on - chip ec/google/chromeec/i2c_tunnel - register "uid" = "1" - register "remote_bus" = "8" - device generic 0.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "uid" = "1" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" - register "property_count" = "2" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - register "property_list[1].type" = "ACPI_DP_TYPE_STRING" - register "property_list[1].name" = ""realtek,mclk-name"" - register "property_list[1].string" = ""oscout1"" - device i2c 1a alias audio_rt5682 on end - end - end - end - chip ec/google/chromeec/audio_codec - register "uid" = "1" - device generic 0 on end - end - end - end - end - end # domain - - device ref i2c_3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" - device i2c 50 on end - end - end - - device ref uart_0 on end # console - -end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb deleted file mode 100644 index 4bb42dea1c..0000000000 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ /dev/null @@ -1,439 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -fw_config - field USB_DAUGHTERBOARD 0 3 end -end - -chip soc/amd/picasso - - # Set FADT Configuration - register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - # See table 5-34 ACPI 6.3 spec - register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" - - # ACP Configuration - register "common_config.acp_config" = "{ - .acp_pin_cfg = I2S_PINS_I2S_TDM, - .acp_i2s_wake_enable = 0, - .acp_pme_enable = 0, - }" - - # Start : OPN Performance Configuration - # (Configuration that is common for all variants) - # For the below fields, 0 indicates use SOC default - - # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time_ms" = "20" - - # Lower die temperature limit - register "thermctl_limit_degreeC" = "100" - - # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit_mA" = "18000" - register "psi0_soc_current_limit_mA" = "12000" - register "vddcr_soc_voltage_margin_mV" = "0" - register "vddcr_vdd_voltage_margin_mV" = "0" - - # VRM Limits - register "vrm_maximum_current_limit_mA" = "0" - register "vrm_soc_maximum_current_limit_mA" = "0" - register "vrm_current_limit_mA" = "0" - register "vrm_soc_current_limit_mA" = "0" - - # Misc SMU settings - register "sb_tsi_alert_comparator_mode_en" = "0" - register "core_dldo_bypass" = "1" - register "min_soc_vid_offset" = "0" - register "aclk_dpm0_freq_400MHz" = "0" - - # End : OPN Performance Configuration - - register "emmc_config" = "{ - .timing = SD_EMMC_EMMC_HS400, - .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, - /* - * The reference design was missing a pull-up on the CMD line. - * This means we can't run at the full 400 kHz. By setting this - * to 1 we run at the slowest frequency possible by the - * controller (~97 kHz). - * - * Boards that have the pull-up should correctly set this. - */ - .init_khz_preset = 1, - }" - - register "has_usb2_phy_tune_params" = "1" - - # Controller0 Port0 Default - register "usb_2_port_tune_params[0]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x03, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x6, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller0 Port1 Default - register "usb_2_port_tune_params[1]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x03, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x6, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller0 Port2 Default - register "usb_2_port_tune_params[2]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x03, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x6, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller0 Port3 Default - register "usb_2_port_tune_params[3]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x03, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x6, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller1 Port0 Default - register "usb_2_port_tune_params[4]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x02, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x5, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Controller1 Port1 Default - register "usb_2_port_tune_params[5]" = "{ - .com_pds_tune = 0x07, - .sq_rx_tune = 0x3, - .tx_fsls_tune = 0x3, - .tx_pre_emp_amp_tune = 0x02, - .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, - .tx_vref_tune = 0x5, - .tx_hsxv_tune = 0x3, - .tx_res_tune = 0x01, - }" - - # Start RV2 USB3 PHY Parameters - register "usb3_phy_override" = "0" - - # USB3 Port0 Default - register "usb3_phy_tune_params[0]" = "{ - .rx_eq_delta_iq_ovrd_val = 0x0, - .rx_eq_delta_iq_ovrd_en = 0x0, - }" - - # USB3 Port1 Default - register "usb3_phy_tune_params[1]" = "{ - .rx_eq_delta_iq_ovrd_val = 0x0, - .rx_eq_delta_iq_ovrd_en = 0x0, - }" - - # USB3 Port2 Default - register "usb3_phy_tune_params[2]" = "{ - .rx_eq_delta_iq_ovrd_val = 0x0, - .rx_eq_delta_iq_ovrd_en = 0x0, - }" - - # USB3 Port3 Default - register "usb3_phy_tune_params[3]" = "{ - .rx_eq_delta_iq_ovrd_val = 0x0, - .rx_eq_delta_iq_ovrd_en = 0x0, - }" - - # SUP_DIG_LVL_OVRD_IN Default - register "usb3_rx_vref_ctrl" = "0x10" - register "usb3_rx_vref_ctrl_en" = "0x00" - register "usb_3_tx_vboost_lvl" = "0x07" - register "usb_3_tx_vboost_lvl_en" = "0x00" - - # SUPX_DIG_LVL_OVRD_IN Default - register "usb_3_rx_vref_ctrl_x" = "0x10" - register "usb_3_rx_vref_ctrl_en_x" = "0x00" - register "usb_3_tx_vboost_lvl_x" = "0x07" - register "usb_3_tx_vboost_lvl_en_x" = "0x00" - - # End RV2 USB3 phy setting - - # USB OC pin mapping - register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 - register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 - register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 - register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 - register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera or internal hub - register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth - - # eSPI Configuration - register "common_config.espi_config" = "{ - .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, - .generic_io_range[0] = { - .base = 0x62, - /* - * Only 0x62 and 0x66 are required. But, this is not supported by - * standard IO decodes and there are only 4 generic I/O windows - * available. Hence, open a window from 0x62-0x67. - */ - .size = 5, - }, - .generic_io_range[1] = { - .base = 0x800, /* EC_HOST_CMD_REGION0 */ - .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ - }, - .generic_io_range[2] = { - .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ - .size = 255, /* EC_MEMMAP_SIZE */ - }, - .generic_io_range[3] = { - .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ - .size = 8, /* 0x200 - 0x207 */ - }, - - .io_mode = ESPI_IO_MODE_QUAD, - .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, - .crc_check_enable = 1, - .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, - .periph_ch_en = 1, - .vw_ch_en = 1, - .oob_ch_en = 0, - .flash_ch_en = 0, - - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), - }" - - register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - - # general purpose PCIe clock output configuration - register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN - register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader - register "gpp_clk_config[2]" = "GPP_CLK_OFF" - register "gpp_clk_config[3]" = "GPP_CLK_OFF" - register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD - register "gpp_clk_config[5]" = "GPP_CLK_OFF" - register "gpp_clk_config[6]" = "GPP_CLK_OFF" - - register "pspp_policy" = "DXIO_PSPP_BALANCED" - - # See AMD 55570-B1 Table 13: PCI Device ID Assignments. - device domain 0 on - subsystemid 0x1022 0x1510 inherit - device ref iommu on end - device ref gpp_bridge_1 on # Wifi - chip drivers/wifi/generic - register "wake" = "GEVENT_8" - device pci 00.0 on end - end - end - device ref gpp_bridge_2 on end # SD - device ref gpp_bridge_6 on end # NVME - device ref internal_bridge_a on - device ref gfx on end # Internal GPU - device ref gfx_hda on end # Display HDA - device ref crypto on end # Crypto Coprocessor - device ref xhci_0 on # USB 3.1 - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 3.3 on end - end - - # The following devices are only enabled on Dali SKUs - chip drivers/usb/acpi - register "desc" = ""User-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" - device usb 2.5 alias xhci0_bt on end - end - end - end - end - device ref xhci_1 on # USB 3.1 - chip drivers/usb/acpi - # The following devices are only enabled on Picasso SKUs - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""User-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" - device usb 2.1 alias xhci1_bt on end - end - chip drivers/usb/acpi - register "desc" = ""World-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.0 on end - end - end - end - end - device ref acp on - chip drivers/amd/i2s_machine_dev - register "hid" = ""AMDI5682"" - # DMIC select GPIO for ACP machine device - # This GPIO is used to select DMIC0 or DMIC1 by the - # kernel driver. It does not really have a polarity - # since low and high control the selection of DMIC and - # hence does not have an active polarity. - # Kernel driver does not use the polarity field and - # instead treats the GPIO selection as follows: - # Set low (0) = Select DMIC0 - # Set high (1) = Select DMIC1 - register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" - device generic 0.0 alias acp_machine on end - end - end # Audio - device ref hda off end # HDA - device ref mp2 on end # non-Sensor Fusion Hub device - end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 alias cros_ec on - chip ec/google/chromeec/i2c_tunnel - register "uid" = "0" - register "remote_bus" = "8" - device generic 0.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "uid" = "1" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_29)" - register "property_count" = "2" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - register "property_list[1].type" = "ACPI_DP_TYPE_STRING" - register "property_list[1].name" = ""realtek,mclk-name"" - register "property_list[1].string" = ""oscout1"" - device i2c 1a alias audio_rt5682 on end - end - end - end - chip ec/google/chromeec/i2c_tunnel - register "name" = ""MSTH"" - register "uid" = "1" - register "remote_bus" = "9" - device generic 1.0 alias cros_ec_i2c_9 on - chip drivers/i2c/generic - register "hid" = ""10EC2141"" - register "name" = ""MSTH"" - register "uid" = "1" - register "desc" = ""Realtek RTD2141B"" - # Device presence is variant-specific - device i2c 4a alias db_mst off end - end - end - end - chip ec/google/chromeec/audio_codec - register "uid" = "1" - device generic 0 on end - end - end - end - end - end # domain - - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" - register "sdmode_delay" = "5" - device generic 0.1 on end - end - - device ref i2c_3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" - device i2c 50 on end - end - end - - device ref uart_0 on end # console - -end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c deleted file mode 100644 index 992d89661f..0000000000 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include - -void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, - size_t *dxio_num, - const fsp_ddi_descriptor **ddi_descs, - size_t *ddi_num) -{ - *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); - *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); -} - -static const fsp_dxio_descriptor dxio_descriptors[] = { - { - // NVME SSD - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 4, - .end_logical_lane = 5, - .device_number = 1, - .function_number = 7, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, - }, - { - // WLAN - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 1, - .function_number = 2, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - }, - { - // SD Reader - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, - } -}; - -const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) -{ - *num = ARRAY_SIZE(dxio_descriptors); - return dxio_descriptors; -} - -const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) -{ - /* Different configurations of dalboz have different ddi configurations. - * Therefore, don't provide any baseboard defaults. */ - *num = 0; - return NULL; -} diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c deleted file mode 100644 index ae36731c7b..0000000000 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ /dev/null @@ -1,184 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, - size_t *dxio_num, - const fsp_ddi_descriptor **ddi_descs, - size_t *ddi_num) -{ - *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); - *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); -} - -/* FP5 package can support Type 1 (Picasso) and Type 2 (Dali), however some - * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. - * Those parts need to be configured as Type 2. */ - -static const fsp_dxio_descriptor pco_dxio_descriptors[] = { - { - // NVME SSD - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 0, - .end_logical_lane = 3, - .device_number = 1, - .function_number = 7, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ4, - }, - { - // WLAN - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 4, - .end_logical_lane = 4, - .device_number = 1, - .function_number = 2, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - }, - { - // SD Reader - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 5, - .end_logical_lane = 5, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, - } -}; - -static const fsp_dxio_descriptor dali_dxio_descriptors[] = { - { - // NVME SSD - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 0, - .end_logical_lane = 1, - .device_number = 1, - .function_number = 7, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ4, - }, - { - // WLAN - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 4, - .end_logical_lane = 4, - .device_number = 1, - .function_number = 2, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - }, - { - // SD Reader - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 5, - .end_logical_lane = 5, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, - } -}; - -const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) -{ - /* Type 2 or Type 1 fused like Type 2. */ - if (soc_is_reduced_io_sku()) { - *num = ARRAY_SIZE(dali_dxio_descriptors); - return dali_dxio_descriptors; - } else { - /* Type 1 */ - *num = ARRAY_SIZE(pco_dxio_descriptors); - return pco_dxio_descriptors; - } - -} - -static const fsp_ddi_descriptor pco_ddi_descriptors[] = { - { - // DDI0, DP0, eDP - .connector_type = EDP, - .aux_index = AUX1, - .hdp_index = HDP1 - }, - { - // DDI1, DP1, DB OPT1 HDMI - .connector_type = HDMI, - .aux_index = AUX2, - .hdp_index = HDP2 - }, - { - // DDI2, DP2, DB OPT1 USB-C1 - .connector_type = DP, - .aux_index = AUX3, - .hdp_index = HDP3, - }, - { - // DDI3, DP3, USB-C0 - .connector_type = DP, - .aux_index = AUX4, - .hdp_index = HDP4, - } -}; - -static const fsp_ddi_descriptor dali_ddi_descriptors[] = { - { - // DDI0, DP0, eDP - .connector_type = EDP, - .aux_index = AUX1, - .hdp_index = HDP1 - }, - { - // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub - .connector_type = DP, - .aux_index = AUX2, - .hdp_index = HDP2 - }, - { - // DDI2, DP3, USB-C0 - .connector_type = DP, - .aux_index = AUX4, - .hdp_index = HDP4, - } -}; - -const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) -{ - /* Type 2 or Type 1 fused like Type 2. */ - if (soc_is_reduced_io_sku()) { - *num = ARRAY_SIZE(dali_ddi_descriptors); - return dali_ddi_descriptors; - } else { - /* Type 1 */ - *num = ARRAY_SIZE(pco_ddi_descriptors); - return pco_ddi_descriptors; - } -} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c deleted file mode 100644 index 5c5933920b..0000000000 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ /dev/null @@ -1,368 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include - -static const struct soc_amd_gpio gpio_set_stage_ram[] = { - /* PWR_BTN_L */ - PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), - /* SYS_RESET_L */ - PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* WIFI_PCIE_WAKE_ODL */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* PEN_DETECT_ODL */ - PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), - /* PEN_POWER_EN - Enabled*/ - PAD_GPO(GPIO_5, HIGH), - /* EN_PWR_TOUCHPAD */ - PAD_GPO(GPIO_6, HIGH), - /* I2S_SDIN */ - PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), - /* I2S_LRCLK - Bit banged in depthcharge */ - PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), - /* TOUCHPAD_INT_ODL */ - PAD_SCI(GPIO_9, PULL_NONE, LEVEL_LOW), - /* S0iX SLP - goes to EC */ - PAD_GPO(GPIO_10, HIGH), - /* EC_IN_RW_OD */ - PAD_GPI(GPIO_11, PULL_NONE), - /* USI_INT_ODL */ - PAD_GPI(GPIO_12, PULL_NONE), - /* GPIO_13 - GPIO_15: Not available */ - /* USB_OC0_L - USB C0/A0 */ - PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* USB_OC1_L - USB C1 */ - PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), - /* WIFI_DISABLE */ - PAD_GPO(GPIO_18, LOW), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* EMMC_CMD */ - PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), - /* EC_FCH_SCI_ODL */ - PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), - /* AC_PRES */ - PAD_NF(GPIO_23, AC_PRES, PULL_UP), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), - /* GPIO_25: Not available */ - /* PCIE_RST0_L - Fixed timings */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* GPIO_27: Configured in bootblock. */ - /* GPIO_28: Not available */ - /* GPIO_29: Handled in bootblock for wifi power/reset control. */ - /* FCH_ESPI_EC_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* EC_AP_INT_ODL (Sensor Framesync) */ - PAD_GPI(GPIO_31, PULL_NONE), - /* EN_PWR_TOUCHSCREEN */ - PAD_GPO(GPIO_32, HIGH), - /* GPIO_33 - GPIO_39: Not available */ - /* NVME_AUX_RESET_L */ - PAD_GPO(GPIO_40, HIGH), - /* GPIO_41: Not available */ - /* GPIO_42: Handled in bootblock for wifi power/reset control. */ - /* GPIO_43 - GPIO_66: Not available */ - /* DMIC_SEL */ - /* - * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash - * access will be very slow. - */ - PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic - /* EMMC_RESET_L */ - PAD_GPO(GPIO_68, HIGH), - /* RAM ID 3 */ - PAD_GPI(GPIO_69, PULL_NONE), - /* EMMC_CLK */ - PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), - /* GPIO_71 - GPIO_73: Not available */ - /* EMMC_DATA4 */ - PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), - /* EMMC_DATA6 */ - PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), - /* EN_PWR_CAMERA */ - PAD_GPO(GPIO_76, HIGH), - /* GPIO_77 - GPIO_83: Not available */ - /* HP_INT_ODL */ - PAD_GPI(GPIO_84, PULL_NONE), - /* APU_EDP_BL_DISABLE */ - PAD_GPO(GPIO_85, LOW), - /* RAM ID 2 - Keep High */ - PAD_GPO(GPIO_86, HIGH), - /* EMMC_DATA7 */ - PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), - /* EMMC_DATA5 */ - PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), - /* GPIO_89 - unused */ - PAD_NC(GPIO_89), - /* RAM ID 1 */ - PAD_GPI(GPIO_90, PULL_NONE), - /* EN_SPKR */ - PAD_GPO(GPIO_91, LOW), - /* CLK_REQ0_L - WIFI */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* GPIO_93 - GPIO_103: Not available */ - /* EMMC_DATA0 */ - PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), - /* EMMC_DATA1 */ - PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), - /* EMMC_DATA2 */ - PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), - /* EMMC_DATA3 */ - PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), - /* EMMC_DS */ - PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), - /* GPIO_110 - GPIO112: Not available */ - /* I2C2_SCL - USI/Touchpad */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA - USI/Touchpad */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* CLK_REQ1_L - SD Card */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L - NVMe */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* GPIO_117 - GPIO_128: Not available */ - /* KBRST_L */ - PAD_NF(GPIO_129, KBRST_L, PULL_NONE), - /* GPIO_130 - GPIO_131: Not available */ - /* RAM ID 0 */ - PAD_GPI(GPIO_132, PULL_NONE), - /* GPIO_133 - GPIO_134: Not available */ - /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ - PAD_GPI(GPIO_135, PULL_NONE), - /* UART0_RXD - DEBUG */ - PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), - /* BIOS_FLASH_WP_ODL */ - PAD_GPI(GPIO_137, PULL_NONE), - /* UART0_TXD - DEBUG */ - PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), - /* DEV_BEEP_BCLK */ - PAD_GPI(GPIO_139, PULL_NONE), - /* TOUCHSCREEN_RESET_L */ - PAD_GPO(GPIO_140, HIGH), - /* USB_HUB_RST_L */ - PAD_GPO(GPIO_141, HIGH), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_142, HIGH), - /* BT_DISABLE */ - PAD_GPO(GPIO_143, LOW), - /* USI_REPORT_EN */ - PAD_GPO(GPIO_144, LOW), -}; - -const struct soc_amd_gpio *baseboard_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(gpio_set_stage_ram); - return gpio_set_stage_ram; -} - -static void wifi_power_reset_configure_active_low_power(void) -{ - /* - * Configure WiFi GPIOs such that: - * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device. - * - Enable power to WiFi using EN_PWR_WIFI_L. - * - Wait for 50ms after power to WiFi is enabled. - * - Deassert WIFI_AUX_RESET. - */ - static const struct soc_amd_gpio v3_wifi_table[] = { - /* WIFI_AUX_RESET */ - PAD_GPO(GPIO_29, HIGH), - /* EN_PWR_WIFI_L */ - PAD_GPO(GPIO_42, LOW), - }; - gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); - - mdelay(50); - gpio_set(GPIO_29, 0); -} - -static void wifi_power_reset_configure_active_high_power(void) -{ - /* - * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET - * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be - * set low before driving it high to trigger a WiFi power cycle to meet PCIe - * requirements. Thus, configure GPIOs such that: - * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device - * - Disable power to WiFi. - * - Wait 10ms for WiFi power to go low. - * - Enable power to WiFi using EN_PWR_WIFI. - * - Deassert WIFI_AUX_RESET. - */ - static const struct soc_amd_gpio v3_wifi_table[] = { - /* WIFI_AUX_RESET */ - PAD_GPO(GPIO_29, HIGH), - /* EN_PWR_WIFI */ - PAD_GPO(GPIO_42, LOW), - }; - gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); - - mdelay(10); - gpio_set(GPIO_42, 1); - mdelay(50); - gpio_set(GPIO_29, 0); -} - -static void wifi_power_reset_configure_v3(void) -{ - if (variant_has_active_low_wifi_power()) - wifi_power_reset_configure_active_low_power(); - else - wifi_power_reset_configure_active_high_power(); -} - -static void wifi_power_reset_configure_pre_v3(void) -{ - /* - * Configure WiFi GPIOs such that: - * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. - * - Disable power to WiFi since GPIO_29 goes high on PWRGOOD but has a glitch on RESET# - * deassertion causing WiFi to enter a bad state. - * - Wait 10ms for WiFi power to go low. - * - Enable power to WiFi using EN_PWR_WIFI. - * - Wait for 50ms after power to WiFi is enabled. - * - Deassert WIFI_AUX_RESET_L. - */ - static const struct soc_amd_gpio pre_v3_wifi_table[] = { - /* WIFI_AUX_RESET_L */ - PAD_GPO(GPIO_42, LOW), - /* EN_PWR_WIFI */ - PAD_GPO(GPIO_29, LOW), - }; - gpio_configure_pads(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table)); - - mdelay(10); - gpio_set(GPIO_29, 1); - mdelay(50); - gpio_set(GPIO_42, 1); -} - -void baseboard_pcie_gpio_configure(void) -{ - static const struct soc_amd_gpio pcie_gpio_table[] = { - /* PCIE_RST1_L - Variable timings (May remove) */ - PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), - /* NVME_AUX_RESET_L */ - PAD_GPO(GPIO_40, HIGH), - /* CLK_REQ0_L - WIFI */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* CLK_REQ1_L - SD Card */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L - NVMe */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_142, HIGH), - }; - - gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); - - /* Deassert PCIE_RST1_L */ - gpio_set(GPIO_27, 1); - - if (variant_uses_v3_schematics()) - wifi_power_reset_configure_v3(); - else - wifi_power_reset_configure_pre_v3(); -} - -__weak void finalize_gpios(int slp_typ) -{ -} - -const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) -{ - *size = 0; - return NULL; -} - -static const struct soc_amd_gpio gpio_sleep_table[] = { - /* S0iX SLP */ - PAD_GPO(GPIO_10, LOW), - /* PCIE_RST1_L */ - PAD_GPO(GPIO_27, LOW), - /* - * On pre-v3 schematics, GPIO_29 is EN_PWR_WIFI. So, setting to high should be no-op. - * On v3+ schematics, GPIO_29 is WIFI_AUX_RESET. Setting to high ensures that PERST# is - * asserted to WiFi device until coreboot reconfigures GPIO_29 on resume path. - */ - PAD_GPO(GPIO_29, HIGH), - /* NVME_AUX_RESET_L */ - PAD_GPO(GPIO_40, LOW), - /* EN_PWR_CAMERA */ - PAD_GPO(GPIO_76, LOW), -}; - -const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) -{ - *size = ARRAY_SIZE(gpio_sleep_table); - return gpio_sleep_table; -} - -static const struct soc_amd_gpio espi_gpio_table[] = { - /* PCIE_RST0_L - Fixed timings */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* FCH_ESPI_EC_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), -}; - -const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(espi_gpio_table); - return espi_gpio_table; -} - -static const struct soc_amd_gpio tpm_gpio_table[] = { - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* EC_IN_RW_OD */ - PAD_GPI(GPIO_11, PULL_NONE), -}; - -const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(tpm_gpio_table); - return tpm_gpio_table; -} - -static const struct soc_amd_gpio early_gpio_table[] = { - /* UART0_RXD - DEBUG */ - PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), - /* UART0_TXD - DEBUG */ - PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), -}; - -const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct soc_amd_gpio romstage_gpio_table[] = { - /* Enable touchscreen, hold in reset */ - /* EN_PWR_TOUCHSCREEN */ - PAD_GPO(GPIO_32, HIGH), - /* TOUCHSCREEN_RESET_L */ - PAD_GPO(GPIO_140, LOW), -}; - -const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(romstage_gpio_table); - return romstage_gpio_table; -} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c deleted file mode 100644 index c789660b8c..0000000000 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ /dev/null @@ -1,417 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include -#include -#include - -static const struct soc_amd_gpio gpio_set_stage_ram[] = { - /* PWR_BTN_L */ - PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), - /* SYS_RESET_L */ - PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* WIFI_PCIE_WAKE_ODL */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* PEN_DETECT_ODL */ - PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), - /* PEN_POWER_EN - Enabled*/ - PAD_GPO(GPIO_5, HIGH), - /* FPMCU_INT_L */ - PAD_SCI(GPIO_6, PULL_NONE, LEVEL_LOW), - /* I2S_SDIN */ - PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), - /* I2S_LRCLK - Bit banged in depthcharge */ - PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), - /* TOUCHPAD_INT_ODL */ - PAD_SCI(GPIO_9, PULL_NONE, LEVEL_LOW), - /* S0iX SLP - goes to EC & FPMCU */ - PAD_GPO(GPIO_10, HIGH), - /* USI_INT_ODL */ - PAD_GPI(GPIO_12, PULL_NONE), - /* EN_PWR_TOUCHPAD_PS2 */ - PAD_GPO(GPIO_13, HIGH), - /* BT_DISABLE */ - PAD_GPO(GPIO_14, LOW), - /* GPIO_15: Not available */ - /* USB_OC0_L - USB C0 + USB A0 */ - PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* USB_OC1_L - USB C1 + USB A1 */ - PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), - /* WIFI_DISABLE */ - PAD_GPO(GPIO_18, LOW), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* EMMC_CMD */ - PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), - /* EC_FCH_SCI_ODL */ - PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), - /* AC_PRES */ - PAD_NF(GPIO_23, AC_PRES, PULL_UP), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), - /* GPIO_25: Not available */ - /* PCIE_RST0_L - Fixed timings */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* PCIE_RST1_L (unused) */ - PAD_NC(GPIO_27), - /* GPIO_28: Not available */ - /* GPIO_29: HP_INT_ODL */ - PAD_GPI(GPIO_29, PULL_NONE), - /* FCH_ESPI_EC_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* EC_AP_INT_ODL (Sensor Framesync) */ - PAD_GPI(GPIO_31, PULL_NONE), - /* GPIO_33 - GPIO_39: Not available */ - /* NVME_AUX_RESET_L */ - PAD_GPO(GPIO_40, HIGH), - /* GPIO_41: Not available */ - /* GPIO_42: Handled in bootblock for wifi power/reset control. */ - /* GPIO_43 - GPIO_66: Not available */ - /* DMIC SEL */ - /* - * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash - * access will be very slow. - */ - PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic - /* EMMC_RESET_L */ - PAD_GPO(GPIO_68, HIGH), - /* FPMCU_BOOT0 */ - PAD_GPO(GPIO_69, LOW), - /* EMMC_CLK */ - PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), - /* GPIO_71 - GPIO_73: Not available */ - /* EMMC_DATA4 */ - PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), - /* EMMC_DATA6 */ - PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), - /* EN_PWR_CAMERA */ - PAD_GPO(GPIO_76, HIGH), - /* GPIO_77 - GPIO_83: Not available */ - /* RAM_ID_4 */ - PAD_GPI(GPIO_84, PULL_NONE), - /* APU_EDP_BL_DISABLE */ - PAD_GPO(GPIO_85, LOW), - /* WIFI_AUX_RESET_L */ - PAD_GPO(GPIO_86, HIGH), - /* EMMC_DATA7 */ - PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), - /* EMMC_DATA5 */ - PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), - /* GPIO_89 - unused */ - PAD_NC(GPIO_89), - /* EN_PWR_TOUCHSCREEN */ - PAD_GPO(GPIO_90, HIGH), - /* EN_SPKR */ - PAD_GPO(GPIO_91, LOW), - /* CLK_REQ0_L - WIFI */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* GPIO_93 - GPIO_103: Not available */ - /* EMMC_DATA0 */ - PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), - /* EMMC_DATA1 */ - PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), - /* EMMC_DATA2 */ - PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), - /* EMMC_DATA3 */ - PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), - /* EMMC_DS */ - PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), - /* GPIO_110 - GPIO112: Not available */ - /* I2C2_SCL - USI/Touchpad */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA - USI/Touchpad */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* CLK_REQ1_L - SD Card */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* RAM_ID_3 */ - PAD_GPI(GPIO_116, PULL_NONE), - /* GPIO_117 - GPIO_119: Not available */ - /* RAM_ID_1 */ - PAD_GPI(GPIO_120, PULL_NONE), - /* RAM_ID_0 */ - PAD_GPI(GPIO_121, PULL_NONE), - /* GPIO_122 - GPIO_128: Not available */ - /* KBRST_L */ - PAD_NF(GPIO_129, KBRST_L, PULL_NONE), - /* EC_IN_RW_OD */ - PAD_GPI(GPIO_130, PULL_NONE), - /* RAM_ID_2 */ - PAD_GPI(GPIO_131, PULL_NONE), - /* CLK_REQ4_L - SSD */ - PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), - /* GPIO_133 - GPIO_134: Not available */ - /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ - PAD_GPI(GPIO_135, PULL_NONE), - /* UART0_RXD - DEBUG */ - PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), - /* BIOS_FLASH_WP_ODL */ - PAD_GPI(GPIO_137, PULL_NONE), - /* UART0_TXD - DEBUG */ - PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), - /* DEV_BEEP_BCLK */ - PAD_GPI(GPIO_139, PULL_NONE), - /* TOUCHSCREEN_RESET_L */ - PAD_GPO(GPIO_140, HIGH), - /* UART1_RXD - FPMCU */ - PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_142, HIGH), - /* UART1_TXD - FPMCU */ - PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), - /* USI_REPORT_EN */ - PAD_GPO(GPIO_144, LOW), -}; - -const struct soc_amd_gpio *baseboard_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(gpio_set_stage_ram); - return gpio_set_stage_ram; -} - -static void wifi_power_reset_configure_active_low_power(void) -{ - /* - * Configure WiFi GPIOs such that: - * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. - * - Enable power to WiFi using EN_PWR_WIFI_L. - * - Wait for >50ms after power to WiFi is enabled. (Time between bootblock & ramstage) - * - WIFI_AUX_RESET_L gets deasserted later in mainboard_configure_gpios in ramstage - */ - static const struct soc_amd_gpio v3_wifi_table[] = { - /* WIFI_AUX_RESET_L */ - PAD_GPO(GPIO_86, LOW), - /* EN_PWR_WIFI_L */ - PAD_GPO(GPIO_42, LOW), - }; - gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); - -} - -static void wifi_power_reset_configure_active_high_power(void) -{ - /* - * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET_L - * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be - * set low before driving it high to trigger a WiFi power cycle to meet PCIe - * requirements. Thus, configura GPIOs such that: - * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device - * - Disable power to WiFi. - * - Wait 10ms for WiFi power to go low. - * - Enable power to WiFi using EN_PWR_WIFI. - * - Deassert WIFI_AUX_RESET_L. - */ - static const struct soc_amd_gpio v3_wifi_table[] = { - /* WIFI_AUX_RESET_L */ - PAD_GPO(GPIO_86, LOW), - /* EN_PWR_WIFI */ - PAD_GPO(GPIO_42, LOW), - }; - gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); - - mdelay(10); - gpio_set(GPIO_42, 1); - mdelay(50); - gpio_set(GPIO_86, 1); -} - -static void wifi_power_reset_configure_v3(void) -{ - if (variant_has_active_low_wifi_power()) - wifi_power_reset_configure_active_low_power(); - else - wifi_power_reset_configure_active_high_power(); -} - -static void wifi_power_reset_configure_pre_v3(void) -{ - /* - * Configure WiFi GPIOs such that: - * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. - * - Disable power to WiFi since GPIO_29 goes high on PWRGOOD but has a glitch on RESET# - * deassertion causing WiFi to enter a bad state. - * - Wait 10ms for WiFi power to go low. - * - Enable power to WiFi using EN_PWR_WIFI. - * - Wait for 50ms after power to WiFi is enabled. - * - Deassert WIFI_AUX_RESET_L. - */ - static const struct soc_amd_gpio pre_v3_wifi_table[] = { - /* WIFI_AUX_RESET_L */ - PAD_GPO(GPIO_42, LOW), - /* EN_PWR_WIFI */ - PAD_GPO(GPIO_29, LOW), - }; - gpio_configure_pads(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table)); - - mdelay(10); - gpio_set(GPIO_29, 1); - mdelay(50); - gpio_set(GPIO_42, 1); -} - -void baseboard_pcie_gpio_configure(void) -{ - static const struct soc_amd_gpio pcie_gpio_table[] = { - /* NVME_AUX_RESET_L */ - PAD_GPO(GPIO_40, HIGH), - /* CLK_REQ0_L - WIFI */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* CLK_REQ1_L - SD Card */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ4_L - SSD */ - PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_142, HIGH), - }; - - gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); - - if (variant_uses_v3_schematics()) - wifi_power_reset_configure_v3(); - else - wifi_power_reset_configure_pre_v3(); -} - -__weak void finalize_gpios(int slp_typ) -{ - if (variant_has_fingerprint() && slp_typ != ACPI_S3) { - - if (fpmcu_needs_delay()) - mdelay(550); - - /* - * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out - * of reset by setting FPMCU_RST_L high 3ms later. - */ - gpio_set(GPIO_32, 1); - mdelay(3); - gpio_set(GPIO_11, 1); - } -} - -static const struct soc_amd_gpio gpio_fingerprint_bootblock_table[] = { - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, LOW), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, LOW), -}; - -static const struct soc_amd_gpio gpio_no_fingerprint_bootblock_table[] = { - /* FPMCU_RST_L */ - PAD_NC(GPIO_11), - /* EN_PWR_FP */ - PAD_NC(GPIO_32), -}; - -const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) -{ - if (variant_has_fingerprint()) { - if (slp_typ == ACPI_S3) - return NULL; - - *size = ARRAY_SIZE(gpio_fingerprint_bootblock_table); - return gpio_fingerprint_bootblock_table; - } - - *size = ARRAY_SIZE(gpio_no_fingerprint_bootblock_table); - return gpio_no_fingerprint_bootblock_table; -} - -static const struct soc_amd_gpio gpio_sleep_table[] = { - /* S0iX SLP */ - PAD_GPO(GPIO_10, LOW), - /* NVME_AUX_RESET_L */ - PAD_GPO(GPIO_40, LOW), - /* EN_PWR_CAMERA */ - PAD_GPO(GPIO_76, LOW), -}; - -static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { - /* NVME_AUX_RESET_L */ - PAD_GPO(GPIO_40, LOW), - /* EN_PWR_CAMERA */ - PAD_GPO(GPIO_76, LOW), - - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, LOW), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, LOW), -}; - -const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) -{ - if (slp_typ == SLP_TYP_S5) { - *size = ARRAY_SIZE(gpio_fp_shutdown_table); - return gpio_fp_shutdown_table; - } - - *size = ARRAY_SIZE(gpio_sleep_table); - return gpio_sleep_table; -} - -static const struct soc_amd_gpio espi_gpio_table[] = { - /* PCIE_RST0_L - Fixed timings */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* FCH_ESPI_EC_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), -}; - -const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(espi_gpio_table); - return espi_gpio_table; -} - -static const struct soc_amd_gpio tpm_gpio_table[] = { - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* EC_IN_RW_OD */ - PAD_GPI(GPIO_130, PULL_NONE), -}; - -const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(tpm_gpio_table); - return tpm_gpio_table; -} - -static const struct soc_amd_gpio early_gpio_table[] = { - /* UART0_RXD - DEBUG */ - PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), - /* UART0_TXD - DEBUG */ - PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), -}; - -const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct soc_amd_gpio romstage_gpio_table[] = { - /* Enable touchscreen, hold in reset */ - /* EN_PWR_TOUCHSCREEN */ - PAD_GPO(GPIO_32, HIGH), - /* TOUCHSCREEN_RESET_L */ - PAD_GPO(GPIO_140, LOW), -}; - -const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(romstage_gpio_table); - return romstage_gpio_table; -} diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/trembyle/Makefile.inc new file mode 100644 index 0000000000..e0c4c90669 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/Makefile.inc @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +all-y += gpio.c +smm-y += gpio.c +ramstage-y += fsps.c + +# APCB Board ID GPIO configuration. +# These GPIOs determine which memory SPD will be used during boot. +# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL +# GPIO_NUMBER: FCH GPIO number +# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO +# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO +# APCB_POPULATE_2ND_CHANNEL: Populates 2nd memory channel in APCB when true. +# Trembyle based boards select 1 or 2 channels based on AGPIO84 +# Dalboz based boards only support 1 channel +APCB_BOARD_ID_GPIO0 = 121 1 0 +APCB_BOARD_ID_GPIO1 = 120 1 0 +APCB_BOARD_ID_GPIO2 = 131 3 0 +APCB_BOARD_ID_GPIO3 = 116 1 0 +APCB_POPULATE_2ND_CHANNEL = true diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb new file mode 100644 index 0000000000..4bb42dea1c --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb @@ -0,0 +1,439 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +fw_config + field USB_DAUGHTERBOARD 0 3 end +end + +chip soc/amd/picasso + + # Set FADT Configuration + register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + # See table 5-34 ACPI 6.3 spec + register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" + + # ACP Configuration + register "common_config.acp_config" = "{ + .acp_pin_cfg = I2S_PINS_I2S_TDM, + .acp_i2s_wake_enable = 0, + .acp_pme_enable = 0, + }" + + # Start : OPN Performance Configuration + # (Configuration that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time_ms" = "20" + + # Lower die temperature limit + register "thermctl_limit_degreeC" = "100" + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin_mV" = "0" + register "vddcr_vdd_voltage_margin_mV" = "0" + + # VRM Limits + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + /* + * The reference design was missing a pull-up on the CMD line. + * This means we can't run at the full 400 kHz. By setting this + * to 1 we run at the slowest frequency possible by the + * controller (~97 kHz). + * + * Boards that have the pull-up should correctly set this. + */ + .init_khz_preset = 1, + }" + + register "has_usb2_phy_tune_params" = "1" + + # Controller0 Port0 Default + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port1 Default + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port2 Default + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port3 Default + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port0 Default + register "usb_2_port_tune_params[4]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port1 Default + register "usb_2_port_tune_params[5]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Start RV2 USB3 PHY Parameters + register "usb3_phy_override" = "0" + + # USB3 Port0 Default + register "usb3_phy_tune_params[0]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port1 Default + register "usb3_phy_tune_params[1]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port2 Default + register "usb3_phy_tune_params[2]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # USB3 Port3 Default + register "usb3_phy_tune_params[3]" = "{ + .rx_eq_delta_iq_ovrd_val = 0x0, + .rx_eq_delta_iq_ovrd_en = 0x0, + }" + + # SUP_DIG_LVL_OVRD_IN Default + register "usb3_rx_vref_ctrl" = "0x10" + register "usb3_rx_vref_ctrl_en" = "0x00" + register "usb_3_tx_vboost_lvl" = "0x07" + register "usb_3_tx_vboost_lvl_en" = "0x00" + + # SUPX_DIG_LVL_OVRD_IN Default + register "usb_3_rx_vref_ctrl_x" = "0x10" + register "usb_3_rx_vref_ctrl_en_x" = "0x00" + register "usb_3_tx_vboost_lvl_x" = "0x07" + register "usb_3_tx_vboost_lvl_en_x" = "0x00" + + # End RV2 USB3 phy setting + + # USB OC pin mapping + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 + register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera or internal hub + register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + + register "pspp_policy" = "DXIO_PSPP_BALANCED" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device ref iommu on end + device ref gpp_bridge_1 on # Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end + device ref gpp_bridge_2 on end # SD + device ref gpp_bridge_6 on end # NVME + device ref internal_bridge_a on + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + + # The following devices are only enabled on Dali SKUs + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" + device usb 2.5 alias xhci0_bt on end + end + end + end + end + device ref xhci_1 on # USB 3.1 + chip drivers/usb/acpi + # The following devices are only enabled on Picasso SKUs + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" + device usb 2.1 alias xhci1_bt on end + end + chip drivers/usb/acpi + register "desc" = ""World-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.0 on end + end + end + end + end + device ref acp on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5682"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 0.0 alias acp_machine on end + end + end # Audio + device ref hda off end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device + end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 alias cros_ec on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "0" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_29)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a alias audio_rt5682 on end + end + end + end + chip ec/google/chromeec/i2c_tunnel + register "name" = ""MSTH"" + register "uid" = "1" + register "remote_bus" = "9" + device generic 1.0 alias cros_ec_i2c_9 on + chip drivers/i2c/generic + register "hid" = ""10EC2141"" + register "name" = ""MSTH"" + register "uid" = "1" + register "desc" = ""Realtek RTD2141B"" + # Device presence is variant-specific + device i2c 4a alias db_mst off end + end + end + end + chip ec/google/chromeec/audio_codec + register "uid" = "1" + device generic 0 on end + end + end + end + end + end # domain + + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + + device ref i2c_3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + + device ref uart_0 on end # console + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c b/src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c new file mode 100644 index 0000000000..ae36731c7b --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/fsps.c @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); +} + +/* FP5 package can support Type 1 (Picasso) and Type 2 (Dali), however some + * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. + * Those parts need to be configured as Type 2. */ + +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 3, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + } +}; + +static const fsp_dxio_descriptor dali_dxio_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 1, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + } +}; + +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_reduced_io_sku()) { + *num = ARRAY_SIZE(dali_dxio_descriptors); + return dali_dxio_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_dxio_descriptors); + return pco_dxio_descriptors; + } + +} + +static const fsp_ddi_descriptor pco_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT1 HDMI + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP2, DB OPT1 USB-C1 + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { + // DDI3, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const fsp_ddi_descriptor dali_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_reduced_io_sku()) { + *num = ARRAY_SIZE(dali_ddi_descriptors); + return dali_ddi_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_ddi_descriptors); + return pco_ddi_descriptors; + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c b/src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c new file mode 100644 index 0000000000..c789660b8c --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/gpio.c @@ -0,0 +1,417 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* PEN_DETECT_ODL */ + PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), + /* PEN_POWER_EN - Enabled*/ + PAD_GPO(GPIO_5, HIGH), + /* FPMCU_INT_L */ + PAD_SCI(GPIO_6, PULL_NONE, LEVEL_LOW), + /* I2S_SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S_LRCLK - Bit banged in depthcharge */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* TOUCHPAD_INT_ODL */ + PAD_SCI(GPIO_9, PULL_NONE, LEVEL_LOW), + /* S0iX SLP - goes to EC & FPMCU */ + PAD_GPO(GPIO_10, HIGH), + /* USI_INT_ODL */ + PAD_GPI(GPIO_12, PULL_NONE), + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_13, HIGH), + /* BT_DISABLE */ + PAD_GPO(GPIO_14, LOW), + /* GPIO_15: Not available */ + /* USB_OC0_L - USB C0 + USB A0 */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* USB_OC1_L - USB C1 + USB A1 */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), + /* WIFI_DISABLE */ + PAD_GPO(GPIO_18, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EMMC_CMD */ + PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), + /* EC_FCH_SCI_ODL */ + PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L (unused) */ + PAD_NC(GPIO_27), + /* GPIO_28: Not available */ + /* GPIO_29: HP_INT_ODL */ + PAD_GPI(GPIO_29, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* EC_AP_INT_ODL (Sensor Framesync) */ + PAD_GPI(GPIO_31, PULL_NONE), + /* GPIO_33 - GPIO_39: Not available */ + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* GPIO_41: Not available */ + /* GPIO_42: Handled in bootblock for wifi power/reset control. */ + /* GPIO_43 - GPIO_66: Not available */ + /* DMIC SEL */ + /* + * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash + * access will be very slow. + */ + PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic + /* EMMC_RESET_L */ + PAD_GPO(GPIO_68, HIGH), + /* FPMCU_BOOT0 */ + PAD_GPO(GPIO_69, LOW), + /* EMMC_CLK */ + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ + /* EMMC_DATA4 */ + PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), + /* EMMC_DATA6 */ + PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, HIGH), + /* GPIO_77 - GPIO_83: Not available */ + /* RAM_ID_4 */ + PAD_GPI(GPIO_84, PULL_NONE), + /* APU_EDP_BL_DISABLE */ + PAD_GPO(GPIO_85, LOW), + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, HIGH), + /* EMMC_DATA7 */ + PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), + /* EMMC_DATA5 */ + PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), + /* GPIO_89 - unused */ + PAD_NC(GPIO_89), + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_90, HIGH), + /* EN_SPKR */ + PAD_GPO(GPIO_91, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ + /* EMMC_DATA0 */ + PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), + /* EMMC_DATA1 */ + PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), + /* EMMC_DATA2 */ + PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), + /* EMMC_DATA3 */ + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* EMMC_DS */ + PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* GPIO_110 - GPIO112: Not available */ + /* I2C2_SCL - USI/Touchpad */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA - USI/Touchpad */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* RAM_ID_3 */ + PAD_GPI(GPIO_116, PULL_NONE), + /* GPIO_117 - GPIO_119: Not available */ + /* RAM_ID_1 */ + PAD_GPI(GPIO_120, PULL_NONE), + /* RAM_ID_0 */ + PAD_GPI(GPIO_121, PULL_NONE), + /* GPIO_122 - GPIO_128: Not available */ + /* KBRST_L */ + PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_NONE), + /* RAM_ID_2 */ + PAD_GPI(GPIO_131, PULL_NONE), + /* CLK_REQ4_L - SSD */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ + /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ + PAD_GPI(GPIO_135, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* DEV_BEEP_BCLK */ + PAD_GPI(GPIO_139, PULL_NONE), + /* TOUCHSCREEN_RESET_L */ + PAD_GPO(GPIO_140, HIGH), + /* UART1_RXD - FPMCU */ + PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), + /* UART1_TXD - FPMCU */ + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), + /* USI_REPORT_EN */ + PAD_GPO(GPIO_144, LOW), +}; + +const struct soc_amd_gpio *baseboard_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + +static void wifi_power_reset_configure_active_low_power(void) +{ + /* + * Configure WiFi GPIOs such that: + * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. + * - Enable power to WiFi using EN_PWR_WIFI_L. + * - Wait for >50ms after power to WiFi is enabled. (Time between bootblock & ramstage) + * - WIFI_AUX_RESET_L gets deasserted later in mainboard_configure_gpios in ramstage + */ + static const struct soc_amd_gpio v3_wifi_table[] = { + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, LOW), + /* EN_PWR_WIFI_L */ + PAD_GPO(GPIO_42, LOW), + }; + gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); + +} + +static void wifi_power_reset_configure_active_high_power(void) +{ + /* + * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET_L + * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be + * set low before driving it high to trigger a WiFi power cycle to meet PCIe + * requirements. Thus, configura GPIOs such that: + * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device + * - Disable power to WiFi. + * - Wait 10ms for WiFi power to go low. + * - Enable power to WiFi using EN_PWR_WIFI. + * - Deassert WIFI_AUX_RESET_L. + */ + static const struct soc_amd_gpio v3_wifi_table[] = { + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, LOW), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_42, LOW), + }; + gpio_configure_pads(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); + + mdelay(10); + gpio_set(GPIO_42, 1); + mdelay(50); + gpio_set(GPIO_86, 1); +} + +static void wifi_power_reset_configure_v3(void) +{ + if (variant_has_active_low_wifi_power()) + wifi_power_reset_configure_active_low_power(); + else + wifi_power_reset_configure_active_high_power(); +} + +static void wifi_power_reset_configure_pre_v3(void) +{ + /* + * Configure WiFi GPIOs such that: + * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. + * - Disable power to WiFi since GPIO_29 goes high on PWRGOOD but has a glitch on RESET# + * deassertion causing WiFi to enter a bad state. + * - Wait 10ms for WiFi power to go low. + * - Enable power to WiFi using EN_PWR_WIFI. + * - Wait for 50ms after power to WiFi is enabled. + * - Deassert WIFI_AUX_RESET_L. + */ + static const struct soc_amd_gpio pre_v3_wifi_table[] = { + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_42, LOW), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, LOW), + }; + gpio_configure_pads(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table)); + + mdelay(10); + gpio_set(GPIO_29, 1); + mdelay(50); + gpio_set(GPIO_42, 1); +} + +void baseboard_pcie_gpio_configure(void) +{ + static const struct soc_amd_gpio pcie_gpio_table[] = { + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ4_L - SSD */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), + }; + + gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); + + if (variant_uses_v3_schematics()) + wifi_power_reset_configure_v3(); + else + wifi_power_reset_configure_pre_v3(); +} + +__weak void finalize_gpios(int slp_typ) +{ + if (variant_has_fingerprint() && slp_typ != ACPI_S3) { + + if (fpmcu_needs_delay()) + mdelay(550); + + /* + * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out + * of reset by setting FPMCU_RST_L high 3ms later. + */ + gpio_set(GPIO_32, 1); + mdelay(3); + gpio_set(GPIO_11, 1); + } +} + +static const struct soc_amd_gpio gpio_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +static const struct soc_amd_gpio gpio_no_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + if (variant_has_fingerprint()) { + if (slp_typ == ACPI_S3) + return NULL; + + *size = ARRAY_SIZE(gpio_fingerprint_bootblock_table); + return gpio_fingerprint_bootblock_table; + } + + *size = ARRAY_SIZE(gpio_no_fingerprint_bootblock_table); + return gpio_no_fingerprint_bootblock_table; +} + +static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), +}; + +static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), + + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) +{ + if (slp_typ == SLP_TYP_S5) { + *size = ARRAY_SIZE(gpio_fp_shutdown_table); + return gpio_fp_shutdown_table; + } + + *size = ARRAY_SIZE(gpio_sleep_table); + return gpio_sleep_table; +} + +static const struct soc_amd_gpio espi_gpio_table[] = { + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + +static const struct soc_amd_gpio early_gpio_table[] = { + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct soc_amd_gpio romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_32, HIGH), + /* TOUCHSCREEN_RESET_L */ + PAD_GPO(GPIO_140, LOW), +}; + +const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- cgit v1.2.3