From 3e314636a63e5f981eb038a2767bd606fea9f468 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 14 Oct 2020 22:27:51 +0200 Subject: soc/intel/skylake/cpu.c: Fix comment coding style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This comment does not follow any of the styles outlined in the coding style page of the documentation. Adjust it to match the preferred style. Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 79fcda1fa5..f1b40f6d01 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -34,10 +34,10 @@ static void configure_isst(void) if (conf->speed_shift_enable) { /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - is supported or not. coreboot needs to configure MSR 0x1AA - which is then reflected in the CPUID register. - */ + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ -- cgit v1.2.3