From 3d5151968543127d3e89a15d25d1a0b6a150f571 Mon Sep 17 00:00:00 2001 From: Terry Chen Date: Wed, 4 May 2022 16:03:12 +0800 Subject: mb/google/brya/var/crota: Fix codec reset pin in overridetree Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64043 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/crota/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index a8b7113d99..b031eec9fa 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -132,7 +132,7 @@ chip soc/intel/alderlake device ref i2c0 on chip drivers/i2c/cs42l42 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B15)" register "ts_inv" = "true" register "ts_dbnc_rise" = "RISE_DEB_1000_MS" register "ts_dbnc_fall" = "FALL_DEB_0_MS" -- cgit v1.2.3